22699 patents
Page 17 of 1135
Utility
Integrated Circuit Structures Having Inverters with Contacts Between Nanowires
28 Dec 23
Structures having inverters with contacts between nanowires are described.
Abhishek Anil SHARMA, Wilfred GOMES
Filed: 28 Jun 22
Utility
Static Random-access Memory Devices with Angled Transistors
28 Dec 23
SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein.
Abhishek A. Sharma, Sagar Suthram, Kimberly L. Pierce, Elliot Tan, Pushkar Sharad Ranade, Shem Odhiambo Ogadhoh, Wilfred Gomes, Anand S. Murthy, Swaminathan Sivakumar, Tahir Ghani
Filed: 5 May 23
Utility
ofrrvl60 kqeubvz7j2rh4fspety2torom3qdugexp
28 Dec 23
Structures having memory with backside DRAM and power delivery are described.
Abhishek Anil SHARMA, Sagar SUTHRAM, Wilfred GOMES, Tahir GHANI, Rishabh MEHANDRU, Cory WEBER, Anand S. MURTHY
Filed: 28 Jun 22
Utility
clog1uwo63x6jz3z5qeyvaugta8k3mhtvillafz
28 Dec 23
A semiconductor structure, system and method.
Shafaat Ahmed, Gowtham Sriram Jawaharram, Cyrus M. Fox, Jose L. Cruz-Campa, Kriti Agarwal, Jian Jiao, Hong Li, Bharat V. Krishnan, Ervin T. Hill, III
Filed: 27 Jun 22
Utility
33coxd4 eqb5ijftclwez
28 Dec 23
Technologies for expanded beam optical connectors are disclosed.
Wesley B. Morgan, Stephen A. Smith, Stephanie J. Arouh, Fan Fan, Jianyong Mo, Henry V. Wladkowski
Filed: 24 Jun 22
Utility
b2rf2wxh28hd1zmpp 948trqvhwtcjktpy52rja8lyb0kfqd90kwxyuhs
28 Dec 23
A liquid metal (LM) dispensing apparatus and method for design and fabrication thereof.
Sangeon Lee, Tingting Gao, Xiao Lu, Matthew T. Magnavita, Jiaqi Wu
Filed: 28 Jun 22
Utility
cvcd df0g3ivatx0id45lbxml
28 Dec 23
Embodiments include apparatuses, methods, and systems for computer assisted or autonomous driving (CA/AD).
Yoshifumi Nishi, David Pidwerbecki, David W. Browning, Mark MacDonald
Filed: 6 Sep 23
Utility
62hgj768xexsdmwayxhx2n4r43nejqk8mo8v2kr37by906
28 Dec 23
An electronic device package comprises a substrate with a first side and a second side opposite the first side; a first conductive feature on the first side and having a first surface; a first dielectric material in contact with the first surface, wherein the first dielectric material has a first composition comprising silicon and nitrogen; a second conductive feature on the second side of the substrate and having a second surface; and a second dielectric material in contact with the second surface, wherein the second dielectric material has a second composition different than the first composition, and wherein a surface roughness of the second surface is greater than a surface roughness of the first surface.
Suddhasattwa Nad, Yi Yang, Jason Steill, Jieying Kong
Filed: 23 Jun 22
Utility
oi6c3c6m75c5asj335lxenn6dhsphowohb7ab3h0uzfu u6
28 Dec 23
An electronic device comprises a substrate layer comprising a first side and an opposing second side, a through hole passing through the substrate layer between the first side and the second side, a first electrical pathway passing from a first position on the first side of the substrate layer, through a first portion of the through hole, to a first corresponding position on the second side of the substrate layer, a second electrical pathway passing from a second position on the first side of the substrate layer, through a second portion of the through hole, to a corresponding second position on the second side of the substrate layer, and an insulation layer between the first electrical pathway and the second electrical pathway within the through hole, wherein the insulation layer electrically isolates the first electrical pathway from the second electrical pathway.
Suddhasattwa Nad, Cemil Serdar Geyik, Jiwei Sun, Jason Steill
Filed: 28 Jun 22
Utility
fpsovrwkrrtl5cprlmngpsq8ldvh1ew9sri0eanwjk7aqhpx yev3u99
28 Dec 23
IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein.
Sagar Suthram, Elliot Tan, Abhishek A. Sharma, Shem Odhiambo Ogadhoh, Wilfred Gomes, Pushkar Sharad Ranade, Anand S. Murthy, Tahir Ghani
Filed: 10 May 23
Utility
v4sa7erz0cv4wv353g2hmi
28 Dec 23
Embodiments herein relate to systems, apparatuses, or processes for creating packages that include one or more memory modules with electrically conductive strips on the side of the memory module to route power or provide a ground to multiple BGA contacts on a side of the memory module coupled with a substrate.
Min Suet LIM, Kavitha NAGARAJAN, Eng Huat GOH, Telesphor KAMGAING
Filed: 24 Jun 22
Utility
5i5p1rq9bnignj5gtpygvs98jf8xmzkti3j lllo1yt36w4c
28 Dec 23
Embodiments of a microelectronic assembly comprise: a package substrate comprising a conductive trace in a dielectric material, the conductive trace surrounded by a conductive structure coupled to a ground connection, the package substrate further comprising metallization layers alternating with dielectric layers of the dielectric material; and an integrated circuit (IC) die coupled to a surface of the package substrate, the IC die being coupled to the conductive trace by a conductive pathway.
Cemil Geyik, Kemal Aygun, Zhiguo Qian, Kristof Kuwawi Darmawikarta, Zhichao Zhang
Filed: 23 Jun 22
Utility
31gwdlut2mcagqsb8vi0gq0fz 6hzuo6
28 Dec 23
Integrated circuit structures having recessed self-aligned deep boundary vias are described.
Mohit HARAN, Sukru YEMENICIOGLU, Pratik PATEL, Charles H. WALLACE, Leonard P. GULER, Conor P. PULS, Makram ABD EL QADER, Tahir GHANI
Filed: 27 Jun 22
Utility
d5qgyjigrki6jvgy0oduo0g4v0eqaav8ggzdy4p2esqj8jomhxmew4r0f
28 Dec 23
Embodiments of a microelectronic assembly comprise an interposer comprising a dielectric material and a pad of conductive material having at least one of a ceramic liner and fin structures; at least two integrated circuit (IC) dies coupled to the interposer; and a bridge die in the interposer conductively coupled to the at least two IC dies.
Sameer Paital, Gang Duan, Srinivas V. Pietambaram, Kristof Kuwawi Darmawikarta, Tchefor Ndukum, Vejayakumaran Padavettan, Pooja Wadhwa, Brandon C. Marin
Filed: 23 Jun 22
Utility
ipk pou0vmgqjixtn2vmyioatqae49vlh0h97
28 Dec 23
Techniques for heat sinks and cold plates for compute systems are disclosed.
Prabhakar SUBRAHMANYAM, Tong Wa CHAO, Ying-Feng PANG, Yi XIA, Rahima K. MOHAMMED, Victor P. POLYANKO, Ridvan A. SAHAN, Guangying ZHANG, Guoliang YING, Chuanlou WANG, Jun LU, Liguang DU, Peng WEI, Xiang QUE
Filed: 6 Mar 21
Utility
992i66wlc8c90796k0a6iuj3731rkno36ik3iipyu1
28 Dec 23
Disclosed herein are microelectronic structures including bridges, and related assemblies and methods.
Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Debendra Mallik
Filed: 7 Sep 23
Utility
i7xebacdjch3vcd596w8uritz4 hjhj
28 Dec 23
Embodiments disclosed herein include electronic packages.
Jieying KONG, Whitney BRYKS, Dilan SENEVIRATNE, Suddhasattwa NAD, Srinivas V. PIETAMBARAM
Filed: 28 Jun 22
Utility
ungupuwc3hrfyuep8 f3z5td13iw2xw2ssqoyl4r4ndwiq4m0j
28 Dec 23
IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate.
Eng Huat Goh, Seok Ling Lim, Hazwani Jaffar, Yean Ling Soon
Filed: 23 Jun 22
Utility
9s3hhzsl8oeskw zh8ciwg9w4dqpx37rsryszysjb42qd0xs2576z2byfh6
28 Dec 23
Embodiments herein relate to systems, apparatuses, techniques or processes for packages that include a die complex with a base die that is coupled with a HDP substrate that in turn is coupled with an mSAP board.
Kavitha NAGARAJAN, Eng Huat GOH, Min Suet LIM, Telesphor KAMGAING, Chee Kheong YOON, Jooi Wah WONG, Chu Aun LIM
Filed: 24 Jun 22
Utility
4k7mdt3968xfxcqq8xvmyzu5wtj8cut8gdqr3
28 Dec 23
Techniques for forming overlay metrology marks are disclosed.
Martin N. Weiss
Filed: 22 Jun 22