11728 patents
Page 13 of 587
Utility
Microelectronic Assemblies Including Solder and Non-solder Interconnects
28 Dec 23
Microelectronic assemblies, related devices and methods, are disclosed herein.
Alois Nitsch, Han-Wen Lin, Yin-Ying Chen, Meng-Chi Lee, Andreas Dost, Hans Gerard Jetten
Filed: 23 Jun 22
Utility
Device-to-device Communication System, Packages, and Package System
28 Dec 23
In various aspects, a device-to-device communication system is provided including a first device and a second device.
Tolga ACIKALIN, Arnaud AMADJIKPE, Brent R. CARLTON, Chia-Pin CHIU, Timothy F. COX, Kenneth P. FOUST, Bryce D. HORINE, Telesphor KAMGAING, Renzhi LIU, Jason A. MIX, Sai VADLAMANI, Tae Young YANG, Zhen ZHOU
Filed: 23 Dec 20
Utility
Package Architecture with Vertical Stacking of Integrated Circuit Dies Having Planarized Edges and Multi-side Routing
28 Dec 23
Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface.
Sagar Suthram, Ravindranath Vithal Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes, Pushkar Sharad Ranade, Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Nitin A. Deshpande
Filed: 22 Jun 22
Utility
Packaged Semiconductor Die with Bumpless Die-package Interface for Bumpless Build-up Layer (Bbul) Packages
28 Dec 23
A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described.
Pramod MALATKAR, Weng Hong TEH, John S. GUZEK, Robert L. SANKMAN
Filed: 11 Sep 23
Utility
Lower Device Access In Stacked Transistor Devices
28 Dec 23
An integrated circuit structure includes a device layer including an upper device above a lower device.
Cheng-Ying Huang, Patrick Morrow, Quan Shi, Rohit Galatage, Nicole K. Thomas, Munzarin F. Qayyum, Jami A. Wiedemer, Gilbert Dewey, Mauro J. Kobrinsky, Marko Radosavljevic, Jack T. Kavalieros
Filed: 23 Jun 22
Utility
Package Architecture of Photonic System with Vertically Stacked Dies Having Planarized Edges
28 Dec 23
Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface.
Sagar Suthram, Ravindranath Vithal Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes, Pushkar Sharad Ranade, Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Nitin A. Deshpande
Filed: 22 Jun 22
Utility
Gate All around Transistors on Alternate Substrate Orientation
28 Dec 23
Semiconductor devices on a substrate with an alternative crystallographic surface orientation.
Ashish Agrawal, Anand Murthy, Jack T. Kavalieros, Rajat K. Paul, Susmita Ghose, Seung Hoon Sung
Filed: 23 Jun 22
Utility
Sige:gab Source or Drain Structures with Low Resistivity
28 Dec 23
Integrated circuit structures having source or drain structures with low resistivity are described.
Debaleena NANDI, Imola ZIGONEANU, Gilbert DEWEY, Anant H. JAHAGIRDAR, Harold W. KENNEL, Pratik PATEL, Anand S. MURTHY, Chi-Hing CHOI, Mauro J. KOBRINSKY, Tahir GHANI
Filed: 27 Jun 22
Utility
Self-aligned Embedded Source and Drain Contacts
28 Dec 23
An integrated circuit structure includes a source or drain region, and a contact for the source or drain region.
Nitesh Kumar, Willy Rachmady, Cheng-Ying Huang, Rohit Galatage, Patrick Morrow, Marko Radosavljevic, Jami A. Wiedemer, Subrina Rafique, Mauro J. Kobrinsky
Filed: 28 Jun 22
Utility
Single Gated 3D Nanowire Inverter for High Density Thick Gate Soc Applications
28 Dec 23
Embodiments disclosed herein include semiconductor devices and methods of forming such devices.
Rahul RAMASWAMY, Walid M. HAFEZ, Tanuj TRIVEDI, Jeong Dong KIM, Ting CHANG, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
Filed: 11 Sep 23
Utility
Diffusion Cut Stressors for Stacked Transistors
28 Dec 23
Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials.
Cheng-Ying Huang, Munzarin F. Qayyum, Nicole K. Thomas, Rohit Galatage, Patrick Morrow, Jami A. Wiedemer, Marko Radosavljevic, Jack T. Kavalieros
Filed: 28 Jun 22
Utility
Self-assembled Monolayer on a Dielectric for Transition Metal Dichalcogenide Growth for Stacked 2D Channels
28 Dec 23
Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation.
Carl H. NAYLOR, Kirby MAXEY, Kevin P. O'BRIEN, Chelsey DOROW, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Matthew V. METZ, Scott B. CLENDENNING, Jiun-Ruey CHEN, Chia-Ching LIN, Carly ROGAN
Filed: 27 Jun 22
Utility
Mobility Improvement In Gate All around Transistors Based on Substrate Orientation
28 Dec 23
Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation.
Seung Hoon Sung, Ashish Agrawal, Jack T. Kavalieros, Rambert Nahm, Natalie Briggs, Susmita Ghose, Glenn Glass, Devin R. Merrill, Aaron A. Budrevich, Shruti Subramanian, Biswajeet Guha, William Hsu, Adedapo A. Oni, Rahul Ramamurthy, Anupama Bowonder, Hsin-Ying Tseng, Rajat K. Paul, Marko Radosavljevic
Filed: 23 Jun 22
Utility
Stacked Single Crystal Transition-metal Dichalcogenide Using Seeded Growth
28 Dec 23
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material.
Carl H. NAYLOR, Kirby MAXEY, Kevin P. O'BRIEN, Chelsey DOROW, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Matthew V. METZ, Scott B. CLENDENNING, Chia-Ching LIN, Carly ROGAN, Arnab SEN GUPTA
Filed: 27 Jun 22
Utility
Varactor Device with Backside Electrical Contact
28 Dec 23
A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region.
Ayan Kar, Kalyan C. Kolluru, Nicholas A. Thomson, Vijaya Bhaskara Neeli, Said Rami, Saurabh Morarka, Karthik Krishaswamy, Mauro J. Kobrinsky
Filed: 24 Jun 22
Utility
Integrated Circuit Structure with Backside Power Staple
28 Dec 23
Integrated circuit structures having backside power staple are described.
Sukru YEMENICIOGLU, Xinning WANG, Nischal ARKALI RADHAKRISHNA, Leonard P. GULER, Mauro J. KOBRINSKY, June CHOI, Pratik PATEL, Tahir GHANI
Filed: 27 Jun 22
Utility
Device, System and Method to Deliver Power with Phase Circuits of an Integrated Circuit Die
28 Dec 23
Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator.
Tamir Salus, Shunjiang Xu, Christopher Schaef
Filed: 28 Jun 22
Utility
2D Layered Gate Oxide
28 Dec 23
Embodiments disclosed herein include transistor devices.
Chelsey DOROW, Sudarat LEE, Kevin P. O'BRIEN, Ande KITAMURA, Ashish Verma PENUMATCHA, Carl H. NAYLOR, Kirby MAXEY, Scott B. CLENDENNING, Uygar E. AVCI, Chia-Ching LIN
Filed: 28 Jun 22
Utility
Technologies for Protocol Execution with Aggregation and Caching
28 Dec 23
Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system.
Matthias Schunter
Filed: 21 Jul 23
Utility
Fabrication of Gate-all-around Integrated Circuit Structures Having Common Metal Gates and Having Gate Dielectrics with an Opposite Polarity Dipole Layer
28 Dec 23
Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described.
Dan S. LAVRIC, Dax M. CRUM, YenTing CHIU, Orb ACTON, David J. TOWNER, Tahir GHANI
Filed: 27 Jun 22