11728 patents
Page 9 of 587
Utility
Gate-all-around Transistor Circuit Modification Using Direct Contact And/or Access Probe Points
4 Jan 24
Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit.
Richard H. Livengood, Muhammad Usman Raza, Waqas Ali, Tahir Malik, Shida Tan, Martin Von Haartman, Mauro Kobrinsky, Amir Raveh, Clifford J. Engle
Filed: 1 Jul 22
Utility
Ue Configured to Determine Remaining Channel Occupancy for Ul Transmission for Shared-spectrum Channel Access
4 Jan 24
Systems and methods for downlink transmission using a wideband unlicensed band carrier in 5G networks are described.
Yongjun Kwak, Lopamudra Kundu, Salvatore Talarico, Yingyang Li
Filed: 16 Aug 23
Utility
Barrier for Minimal Underfill Keep-out Zones
4 Jan 24
An integrated circuit (IC) device package substrate comprises a plurality of first interconnect features to couple to a first IC die, a plurality of second interconnect features to couple to a second IC die, and one or more barrier features on a surface of the substrate.
Xavier F. Brun, Jonas G. Croissant
Filed: 1 Jul 22
Utility
Methods and Apparatus for Team Classification In Sports Analysis
4 Jan 24
An example apparatus includes processor circuitry to extract features from image data obtained from a plurality of cameras, the extraction of features performed using a plurality of sequential neural network layers; in response to each of the plurality of sequential neural network layer extracting the features, identify the extracted features in a torso region of the image data via a plurality of attention modules; estimate body landmarks from image data to localize an area; generate an upper heatmap mask based on a geometric center of the image data; calculate a loss function for the image data based on a cross-entropy loss, a pixel-wise loss, and a triplet loss determined from the extracted features and the generated heatmap mask; select lowest correlated classes based on calculated correlations between pairs of a plurality of classes; and calculate voting scores for groups associated with the lowest correlated classes.
Chenning Liu, Qiang Li, Wenlong Li, Yikai Fang, Hang Zheng, Jiansheng Chen
Filed: 23 Sep 21
Utility
Fiducial Marks for Verifying Alignment Accuracy of Bonded Integrated Circuit Dies
4 Jan 24
An integrated circuit (IC) device comprises a host component and an IC die directly bonded to the host component.
Dimitrios Antartis, Nitin A. Deshpande, Siyan Dong, Omkar Karhade, Gwang-soo Kim, Shawna Liff, Siddhartha Mal, Debendra Mallik, Khant Minn, Haris Khan Niazi, Arnab Sarkar, Yi Shi, Botao Zhang
Filed: 1 Jul 22
Utility
Package Heaters for Cold Temperature Operation and Method
4 Jan 24
A semiconductor package comprises two or more dies including at least one integrated circuit.
Ganesh Kondapuram, Chetan Rawal, Kevin Connolly, Robert Anderson
Filed: 30 Jun 22
Utility
Microelectronic Assemblies Including Stacked Dies Coupled by a Through Dielectric Via
4 Jan 24
Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods.
Stephen Morein, Ravindranath Vithal Mahajan, Prashant Majhi
Filed: 30 Jun 22
Utility
Methods and Apparatus to Adhere a Dielectric to a Nonconductive Layer In Circuit Devices
4 Jan 24
Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices.
Kristof Darmawikarta, Srinivas Pietambaram, Benjamin Duong, Haobo Chen
Filed: 30 Jun 22
Utility
Offset Interposers for Large-bottom Packages and Large-die Package-on-package Structures
4 Jan 24
An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA.
Russell K. MORTENSEN, Robert M. NICKERSON, Nicholas R. WATTS
Filed: 14 Sep 23
Utility
Pocketed Copper In First Layer Interconnect and Method
4 Jan 24
A substrate package comprises a substrate comprised of buildup layers.
Suddhasattwa Nad, Jeremy D. Ecton, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jason Steill, Yi Yang, Marcel Arlan Wall
Filed: 1 Jul 22
Utility
Independent Gate Stack for Single Nanowire Standard Cell Transistors
4 Jan 24
Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory.
Abhishek Sharma, Tahir Ghani, Wilfred Gomes, Anand Murthy
Filed: 1 Jul 22
Utility
Shield to Reduce Substrate Electromagnetic Interference and Warpage
4 Jan 24
Embodiments herein relate to systems, apparatuses, techniques, or processes for stiffeners for a surface of a package substrate, where the stiffeners provide EMI/RFI shielding for signal traces or other electrical routings within the package, and in particular for traces at a surface of the package such as microstrip routings.
Telesphor KAMGAING, Chu Aun LIM, Eng Huat GOH, Min Suet LIM, Kavitha NAGARAJAN, Jooi Wah WONG, Chee Kheong YOON
Filed: 29 Jun 22
Utility
Source and Drain Refractory Metal Cap
4 Jan 24
Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein.
Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
Filed: 1 Jul 22
Utility
Semiconductor Package with Extended Stiffener
4 Jan 24
A semiconductor package including: a package substrate including a base die disposed on a top surface of the package substrate, the base die including a plurality of electrical components disposed on a top surface of the base die, the plurality of electrical components including a first electrical component configured adjacent to a second electrical component, wherein the first electrical component and the second electrical component have an asymmetric form-factor; and a stiffener including: a stiffener main portion, wherein the stiffener main portion is affixed to the top surface of the package substrate and configured at least partially surrounding the base die; and a stiffener extension portion configured to extend from the stiffener main portion to be disposed at least partially over the top surface of the base die adjacent to the first electrical component and the second electrical component.
Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Kooi Chi OOI
Filed: 4 Jul 22
Utility
Gate Spacer In Stacked Gate-all-around (Gaa) Device Architecture
4 Jan 24
An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region.
Cheng-Ying Huang, Kai Loon Cheong, Pooja Nath, Susmita Ghose, Rambert Nahm, Natalie Briggs, Charles C. Kuo, Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Jack T. Kavalieros, Thoe Michaelos, David Kohen
Filed: 30 Jun 22
Utility
Semiconductor Packages for Alternate Stacked Memory and Methods of Manufacturing the Same
4 Jan 24
A semiconductor package includes a silicon die including a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface, and a mold layer including a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further including a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface.
Seok Ling LIM, Jenny Shio Yin ONG, Bok Eng CHEAH, Jackson Chung Peng KONG, Kooi Chi OOI
Filed: 4 Jul 22
Utility
Device, Method and System to Provide Epitaxial Structures Opposite Sides of a Separation Layer Between Channel Stacks
4 Jan 24
Techniques and mechanisms for providing epitaxial structures of an integrated circuit (IC).
Abhishek Sharma, Anand Murthy, Tahir Ghani, Wilfred Gomes
Filed: 1 Jul 22
Utility
Alternating Sacrificial Layer Materials for Mechanically Stable 2D Nanoribbon Etch
4 Jan 24
Embodiments disclosed herein include transistors and methods of forming transistors.
Chelsey DOROW, Kevin P. O'BRIEN, Sudarat LEE, Ande KITAMURA, Ashish Verma PENUMATCHA, Carl H. NAYLOR, Kirby MAXEY, Chia-Ching LIN, Scott B. CLENDENNING, Uygar E. AVCI
Filed: 29 Jun 22
Utility
Integrated Clock Gate with Circuitry to Facilitate Clock Frequency Division
4 Jan 24
Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality.
Steven Hsu, Amit Agarwal, Simeon Realov, Mark Anders, Ram Krishnamurthy
Filed: 1 Jul 22
Utility
Voltage Contrast Structure for Trench Connectors
4 Jan 24
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for electrically coupling components of a transistor structure together in order to perform a voltage contrast test to determine opens and shorts within the transistor structure.
Xiao WEN, Dipto THAKURTA, Sairam SUBRAMANIAN, Manish SHARMA
Filed: 30 Jun 22