11728 patents
Page 8 of 587
Utility
Bidirectional Compact Deep Fusion Networks for Multimodality Visual Analysis Applications
4 Jan 24
Techniques related to bidirectional compact deep fusion networks for multimodal image inputs are discussed.
Dongqi CAI, Anbang YAO, Yikai WANG, Ming LU, Yurong CHEN
Filed: 19 Nov 20
Utility
Semiconductor Packages for Stacked Memory-on-package (Smop) and Methods of Manufacturing the Same
4 Jan 24
A semiconductor package includes a package substrate, a base die including a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface, and a first device including a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface.
Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Kooi Chi OOI
Filed: 4 Jul 22
Utility
Detecting Laser-injected Faults
4 Jan 24
An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander.
Minki Cho, Daniel Nemiroff, Carlos Tokunaga, James W. Tschanz, Kah Meng Yeem, Yaxin Shui
Filed: 1 Jul 22
Utility
Semiconductor Package, Base Station, Mobile Device and Method for Forming a Semiconductor Package
4 Jan 24
A semiconductor package is provided.
Ellis NEASE, Giacomo CASCIO, Marc Jan Georges TIEBOUT
Filed: 30 Jun 22
Utility
Poly-scale Kernel-wise Convolution for High-performance Visual Recognition Applications
4 Jan 24
Techniques related to poly-scale kernel-wise convolutional neural network layers are discussed.
Anbang Yao, Xiao Zhou, Guangli Zhang, Yu Zhang, Dian Gu
Filed: 7 Sep 20
Utility
Integrated Circuit Structures Having Raised Epitaxy on Channel Transistor
4 Jan 24
Structures having raised epitaxy on channel structure transistors are described.
Abhishek Anil SHARMA, Tahir GHANI, Rishabh MEHANDRU, Anand S. MURTHY, Wilfred GOMES, Cory WEBER, Sagar SUTHRAM
Filed: 30 Jun 22
Utility
Embedded Die on Interposer Packages
4 Jan 24
Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein.
John S. GUZEK
Filed: 15 Sep 23
Utility
Back-end-of-line 2D Transistor
4 Jan 24
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell.
Chia-Ching LIN, Shriram SHIVARAMAN, Kevin P. O'BRIEN, Ashish Verma PENUMATCHA, Chelsey DOROW, Kirby MAXEY, Carl H. NAYLOR, Sudarat LEE, Uygar E. AVCI
Filed: 30 Jun 22
Utility
Metallization Surface Treatment for Integrated Circuit Packages
4 Jan 24
High-density IC die package routing structures with one or more nitrided surfaces.
Suddhasattwa Nad, Srinivas Pietambaram, Rahul Manepalli, Marcel Wall, Darko Grujicic
Filed: 1 Jul 22
Utility
Technology to Resolve Connector Damage Due to Arcing
4 Jan 24
Systems, apparatuses and methods may provide for power adapter technology that includes an adapter plug having a housing, a plurality of contacts positioned within the housing, wherein the plurality of contacts includes one or more configuration channel contacts, and a piezoelectric membrane positioned on an external surface of the housing, wherein the piezoelectric membrane is electrically connected to the one or more configuration channel contacts.
Navneet Kumar Singh, Shailendra Singh Chauhan, Aiswarya Pious, Amarjeet Kumar, Samarth Alva
Filed: 29 Jun 22
Utility
Microelectronic Assemblies Including Stacked Dies Coupled by a Through Dielectric Via
4 Jan 24
Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods.
Stephen Morein, Ravindranath Vithal Mahajan, Prashant Majhi
Filed: 30 Jun 22
Utility
Multi-gain-step digital step attenuator
4 Jan 24
A digital step attenuator for automatic gain control in a transceiver front-end.
Martin CLARA, Giacomo CASCIO, Erfan GHADERI, Marc Jan Georges TIEBOUT
Filed: 30 Jun 22
Utility
Die-stacked and Molded Architecture for Memory on Package (Mop)
4 Jan 24
An electronic device includes a package substrate; a memory integrated circuit (IC) mounted on the package substrate; a mold layer including one or more chiplets and a base IC die within the mold layer, the one or more chiplets arranged on the base IC die; a top chiplet mounted on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC; and a heat spreader having a uniform surface contacting the memory IC and the top chiplet.
Seok Ling Lim, Chan Kim Lee, Eng Huat Goh, Jenny Shio Yin Ong, Tin Poay Chuah
Filed: 29 Jun 22
Utility
Converged Charging for Edge Enabling Resource Usage and Application Context Transfer
4 Jan 24
Various embodiments herein are directed to solutions for converged charging for edge enabling infrastructure resource usage, application context transfer, and aggregated fifth-generation system (5GS) usage.
Yizhi YAO, Joey CHOU
Filed: 11 Feb 22
Utility
Liquid Metal Based First Level Interconnects
4 Jan 24
In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate.
Kyle J. Arrington, Karumbu Nathan Meyyappan, Srikant Nekkanty
Filed: 2 Jul 22
Utility
Methods, Systems, Articles of Manufacture and Apparatus to Optimize Resources In Edge Networks
4 Jan 24
Methods, apparatus, systems, and articles of manufacture are disclosed to optimize resources in edge networks.
Nilesh Jain, Rajesh Poornachandran, Eriko Nurvitadhi, Anahita Bhiwandiwalla, Juan Pablo Munoz, Ravishankar Iyer, Chaunte W. Lacewell
Filed: 25 Jun 21
Utility
Alignment Via-pad and Via-plane Structures
4 Jan 24
Disclosed herein are via-trace-via structures with improved alignment, and related devices and methods.
Veronica Aleman Strong, Aleksandar Aleksov
Filed: 1 Jul 22
Utility
Dynamic Quantization of Artificial Intelligence or Machine Learning Models In a Radio Access Network
4 Jan 24
A wireless communication device including a memory configured to store instructions; a processor coupled to the memory configured to execute the instructions stored on the memory, wherein the instructions are configured to receive a request message to update a radio access network (RAN) quantization scheme; determine an updated quantization scheme based on properties of a RAN; determine if the updated quantization scheme satisfies a RAN performance criterion; and generate a message including instructions for the updated quantization scheme.
Vaibhav SINGH, Christian MACIOCCO
Filed: 26 Aug 22
Utility
Build Up Material Architecture for Microelectronic Package Device
4 Jan 24
Microelectronic integrated circuit package structures include a first layer over a substrate, the first layer having a matrix material and a filler material within the matrix material.
Jieying Kong, Peumie Abeyratne Kuragama, Ala Omer, Ao Wang, Dilan Seneviratne
Filed: 1 Jul 22
Utility
Method and Apparatus for Real Time, In-situ Immersion Coolant Characterization and Filtration System Control In Response Thereto
4 Jan 24
A method is described.
Je-Young CHANG, Rajiv MONGIA, Sandeep AHUJA
Filed: 28 Aug 23