11728 patents
Page 10 of 587
Utility
In-situ Multi-layer Dielectric Films for Application As Gate Spacer and Etch Stop Layers
4 Jan 24
Embodiments disclosed herein include a transistor and methods of making a transistor.
Walter CASPER, IV, Sudipto NASKAR, Marci Kahiehie Mi Hyon KANG, Weimin HAN, Vivek THIRTHA, Jianqiang LIN
Filed: 29 Jun 22
Utility
Edge Delamination and Crack Prevention Methods for Sinx and Ti-cu Enabled Packages
4 Jan 24
Embodiments disclosed herein include package substrates and methods of forming such substrates.
Suddhasattawa NAD, Rahul N. MANEPALLI, Gang DUAN, Srinivas V. PIETAMBARAM, Yi YANG, Marcel WALL, Darko GRUJICIC, Haobo CHEN, Aaron GARELICK
Filed: 29 Jun 22
Utility
Substrates Having Adhesion Promotor Layers and Related Methods
4 Jan 24
Substrate assemblies having adhesion promotor layers and related methods are disclosed.
Yi Yang, Srinivas Pietambaram, Darko Grujicic, Marcel Wall, Suddhasattwa Nad, Ala Omer, Brian P. Balch, Wei Wei
Filed: 30 Jun 22
Utility
Integrated Circuit Structures Having Vertical Keeper or Power Gate for Backside Power Delivery
4 Jan 24
Structures having vertical keeper or power gate for backside power delivery are described.
Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Cory WEBER, Rishabh MEHANDRU, Wilfred GOMES, Sagar SUTHRAM
Filed: 30 Jun 22
Utility
Passive Circuit on a Back-end-of-line of a Package
4 Jan 24
Embodiments herein relate to systems, apparatuses, or processes directed to fabricating passive circuits on a surface of a BEOL of a package, for example on a C4 connection layer of the BEOL.
Qiang YU, Georgios C. DOGIAMIS, Gwang-Soo KIM, Ibukunoluwa MOMSON, Ali FARID, Said RAMI
Filed: 29 Jun 22
Utility
Integrated Circuit Structures Having Ultra-high Conductivity Global Routing
4 Jan 24
Structures having ultra-high conductivity global routing are described.
Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Sagar SUTHRAM, Pushkar RANADE, Wilfred GOMES, Rishabh MEHANDRU, Cory WEBER
Filed: 30 Jun 22
Utility
Contact Architecture for 2D Stacked Nanoribbon Transistor
4 Jan 24
Embodiments disclosed herein include transistors and methods of forming transistors.
Ashish Verma PENUMATCHA, Kevin P. O'BRIEN, Kirby MAXEY, Carl H. NAYLOR, Chelsey DOROW, Uygar E. AVCI, Matthew V. METZ, Sudarat LEE, Chia-Ching LIN, Sean T. MA
Filed: 30 Jun 22
Utility
Amorphization and Regrowth of Source-drain Regions from the Bottom-side of a Semiconductor Assembly
4 Jan 24
A device is disclosed.
Aaron LILAK, Rishabh MEHANDRU, Willy RACHMADY, Harold KENNEL, Tahir GHANI
Filed: 13 Sep 23
Utility
Mode Select for Multi-frequency Oscillators
4 Jan 24
An apparatus, system, and method for multi-frequency oscillator control are provided.
Timo Huusari, Mohamed A. Abdelmoneum, Brent R. Carlton, Somnath Kundu, Hao Luo, Sarah Shahraini, Jason Mix, Eduardo Alban
Filed: 30 Jun 22
Utility
Method and Apparatus for Automatic Gain Control
4 Jan 24
A method and apparatus for automatic gain control (AGC).
Gregory CHANCE, Peter PAWLIUK
Filed: 30 Jun 22
Utility
Device and method for reconfigurable common-mode feedback control in a receiver front end
4 Jan 24
A radio frequency front-end (RF-FE) device with a reconfigurable common-mode feedback control.
Martin CLARA, Giacomo CASCIO, Erfan GHADERI, Marc Jan Georges TIEBOUT
Filed: 29 Jun 22
Utility
Integrated Circuit Structures Having Vertical Transistor
4 Jan 24
Structures having vertical transistors are described.
Abhishek Anil SHARMA, Rishabh MEHANDRU, Sagar SUTHRAM, Cory WEBER, Tahir GHANI, Anand S. MURTHY, Pushkar RANADE, Wilfred GOMES
Filed: 30 Jun 22
Utility
Stacked Transceiver and Waveguide Launcher Array
4 Jan 24
Embodiments herein relate to systems, apparatuses, or processes for packages that include transceivers that are at least partly positioned underneath a waveguide launcher array to decrease the maximum signal transmission time between the transceiver and the waveguide launcher array.
Georgios C. DOGIAMIS, Neelam PRABHU GAUNKAR, Nada SEKELJIC
Filed: 29 Jun 22
Utility
Composite Printed Circuit Boards and Devices
4 Jan 24
The present disclosure is directed to a printed circuit board having a composite upper surface with a first section of a first-type of printed circuit board and a second section of a second-type of printed circuit board, for which the first section of the first-type of printed circuit board and the second section of the second-type of printed circuit board are coupled, respectively, to at least one device that is configured to abridge the first and second sections of the composite upper surface.
Howe Yin LOO, Tin Poay CHUAH, Jenny Shio Yin ONG, Chee Min LOH, Bok Eng CHEAH, Jackson Chung Peng KONG, Seok Ling LIM, Kooi Chi OOI
Filed: 4 Jul 22
Utility
Method and System for Digital Background Offset Correction
of a Comparator In an Analog-to-digital Converter
4 Jan 24
A multi-step analog-to-digital converter (ADC).
Michael FULDE, Harneet KHURANA, Matteo CAMPONESCHI, Patrizia GRECO, Christian LINDHOLM, Martin CLARA, Giacomo CASCIO
Filed: 29 Jun 22
Utility
Device-specific Connections In an Information Centric Network
4 Jan 24
System and techniques for device-specific connections in an information centric network (ICN) are described herein.
Rustam Pirmagomedov, Srikathyayani Srikanteswara, Felipe Andrés Tampier Jara, Gabriel Arrobo, Dmistri Moltchanov, Yi Zhang, Nageen Himayat, Sergey Andreev, Yevgeni Koucheryavy
Filed: 3 Nov 21
Utility
Integrated Circuit Structures Having Memory Access Transistor with Backside Contact
4 Jan 24
Structures having memory access transistors with backside contacts are described.
Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Wilfred GOMES, Cory WEBER, Rishabh MEHANDRU, Sagar SUTHRAM, Pushkar RANADE
Filed: 30 Jun 22
Utility
Vertical Interconnect Design for Improved Electrical Performance
4 Jan 24
The present disclosure is directed to a printed circuit board having a first surface and providing a signal pathway using a plurality of plated through hole (PTH) vias including a first set of PTH vias having a first PTH via coupled to a second PTH via and a first vertical separator being configured therebetween, with the first vertical separator extending a first depth from the first surface, and a second set of PTH vias having a third PTH via coupled to a fourth PTH via and a second vertical separator being configured therebetween, with the second vertical separator extending a second depth from the first surface, and a connector trace coupling the second PTH via to the third PTH via being positioned at a third depth from the first surface, for which the third depth is less than the first depth or the second depth.
Jackson Chung Peng KONG, Bok Eng CHEAH, Kok Hou TEH
Filed: 4 Jul 22
Utility
Large Grain and Halogen-free Silicon Cell Channel for 3D Nand String
28 Dec 23
An example of an apparatus may include an array of linear cell channels and a string of NAND memory cells arranged along a cell channel of the array of linear cell channels, where a polysilicon cell channel layer comprises material with less than E17 halogen atoms per cubic centimeter, where a thickness of the polysilicon cell channel layer is less than or equal to 25 nanometers, and where an area-weighted grain height mean of the polysilicon cell channel layer is greater than 30 nanometers.
Jessica S. Kachian
Filed: 12 Sep 23
Utility
Cold Plates for Secondary Side Components of Printed Circuit Boards
28 Dec 23
Cold plates for secondary side components of printed circuit boards are disclosed herein.
Prabhakar Subrahmanyam, Tejas J. Shah, Yi Xia, Ying-Feng Pang, Mark Lawrence Bianco, Vishnu Prasadh Sugumar, Vikas Kundapura Rao, Srinivasa Rao Damaraju, Ridvan Amir Sahan, Emad Shehadeh Al-Momani, Rahima Khatun Mohammed, Mirui Wang, Devdatta Prakash Kulkarni
Filed: 29 Jun 23