11728 patents
Page 12 of 587
Utility
Technologies for Overlay Metrology Marks
28 Dec 23
Techniques for forming overlay metrology marks are disclosed.
Martin N. Weiss
Filed: 22 Jun 22
Utility
Slotted Stiffener for a Package Substrate
28 Dec 23
Embodiments herein relate to systems, apparatuses, or processes directed to a stiffener for a surface of a semiconductor package, where the stiffener includes slots that allow a gasket to go over the stiffener to electrically couple with a ground or a VSS of the semiconductor package.
Kavitha NAGARAJAN, Eng Huat GOH, Min Suet LIM, Telesphor KAMGAING, Chee Kheong YOON, Jooi Wah WONG, Chu Aun LIM
Filed: 24 Jun 22
Utility
Package Architecture with Vertically Stacked Bridge Dies Having Planarized Edges
28 Dec 23
Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces.
Sagar Suthram, Ravindranath Vithal Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes, Pushkar Sharad Ranade, Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Nitin A. Deshpande
Filed: 22 Jun 22
Utility
Package Architecture of Three-dimensional Interconnect Cube with Integrated Circuit Dies Having Planarized Edges
28 Dec 23
Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface.
Sagar Suthram, Ravindranath Vithal Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes, Pushkar Sharad Ranade, Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Nitin A. Deshpande, Joshua Fryman, Stephen Morein, Matthew Adiletta
Filed: 22 Jun 22
Utility
Package Architecture with Vertical Stacking of Integrated Circuit Dies Having Planarized Edges and Multi-side Routing
28 Dec 23
Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface.
Sagar Suthram, Ravindranath Vithal Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes, Pushkar Sharad Ranade, Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Nitin A. Deshpande
Filed: 22 Jun 22
Utility
Single Gated 3D Nanowire Inverter for High Density Thick Gate Soc Applications
28 Dec 23
Embodiments disclosed herein include semiconductor devices and methods of forming such devices.
Rahul RAMASWAMY, Walid M. HAFEZ, Tanuj TRIVEDI, Jeong Dong KIM, Ting CHANG, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
Filed: 11 Sep 23
Utility
Mobility Improvement In Gate All around Transistors Based on Substrate Orientation
28 Dec 23
Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation.
Seung Hoon Sung, Ashish Agrawal, Jack T. Kavalieros, Rambert Nahm, Natalie Briggs, Susmita Ghose, Glenn Glass, Devin R. Merrill, Aaron A. Budrevich, Shruti Subramanian, Biswajeet Guha, William Hsu, Adedapo A. Oni, Rahul Ramamurthy, Anupama Bowonder, Hsin-Ying Tseng, Rajat K. Paul, Marko Radosavljevic
Filed: 23 Jun 22
Utility
Stacked Single Crystal Transition-metal Dichalcogenide Using Seeded Growth
28 Dec 23
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material.
Carl H. NAYLOR, Kirby MAXEY, Kevin P. O'BRIEN, Chelsey DOROW, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Matthew V. METZ, Scott B. CLENDENNING, Chia-Ching LIN, Carly ROGAN, Arnab SEN GUPTA
Filed: 27 Jun 22
Utility
Varactor Device with Backside Electrical Contact
28 Dec 23
A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region.
Ayan Kar, Kalyan C. Kolluru, Nicholas A. Thomson, Vijaya Bhaskara Neeli, Said Rami, Saurabh Morarka, Karthik Krishaswamy, Mauro J. Kobrinsky
Filed: 24 Jun 22
Utility
2D Layered Gate Oxide
28 Dec 23
Embodiments disclosed herein include transistor devices.
Chelsey DOROW, Sudarat LEE, Kevin P. O'BRIEN, Ande KITAMURA, Ashish Verma PENUMATCHA, Carl H. NAYLOR, Kirby MAXEY, Scott B. CLENDENNING, Uygar E. AVCI, Chia-Ching LIN
Filed: 28 Jun 22
Utility
Device, System and Method to Deliver Power with Phase Circuits of an Integrated Circuit Die
28 Dec 23
Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator.
Tamir Salus, Shunjiang Xu, Christopher Schaef
Filed: 28 Jun 22
Utility
Integrated Circuit Structure with Backside Power Staple
28 Dec 23
Integrated circuit structures having backside power staple are described.
Sukru YEMENICIOGLU, Xinning WANG, Nischal ARKALI RADHAKRISHNA, Leonard P. GULER, Mauro J. KOBRINSKY, June CHOI, Pratik PATEL, Tahir GHANI
Filed: 27 Jun 22
Utility
Packet Processing with Reduced Latency
28 Dec 23
Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency.
Eliezer Tamir, Jesse C. Brandeburg, Anil Vasudevan
Filed: 8 Sep 23
Utility
Secure Stream Protocol for Serial Interconnect
28 Dec 23
Methods, systems, and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed.
Vedvyas Shanbhogue, Siddhartha Chhabra, David J. Harriman, Raghunandan Makaram, Ioannis T. Schoinas
Filed: 30 Jun 23
Utility
Methods and Arrangements for Short Beacon Frames In Wireless Networks
28 Dec 23
Embodiments provide a new short beacon frame format and its operation with full beacon frame transmissions for wireless communications devices.
MINYOUNG PARK, ADRIAN P. STEPHENS, THOMAS J. KENNEY, EMILY H. QI
Filed: 6 Sep 23
Utility
Technologies for Accelerated HTTP Processing with Hardware Acceleration
28 Dec 23
Technologies for accelerated HTTP message processing include a computing device having a network controller.
Parthasarathy Sarangam, Manasi Deval, Gregory Bowers
Filed: 26 May 23
Utility
Technologies for Protocol Execution with Aggregation and Caching
28 Dec 23
Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system.
Matthias Schunter
Filed: 21 Jul 23
Utility
Organic Adhesion Promotor for Dielectric Adhesion to a Copper Trace
28 Dec 23
Embodiments herein relate to systems, apparatuses, or processes directed to an organic adhesion promoter layer on the surface of a copper trace to reduce delamination between a dielectric material and the surface of the copper trace, and to facilitate a smooth surface interface between the surface of the copper trace and of a copper feature, such as a copper-filled via, placed on the surface of the copper trace.
Yi YANG, Srinivas V. PIETAMBARAM, Suddhasattwa NAD, Darko GRUJICIC, Marcel WALL
Filed: 24 Jun 22
Utility
Packaging Architecture with Rounded Traces for On-package High-speed Interconnects
28 Dec 23
Embodiments of a microelectronic assembly comprise: a package substrate having a first face and an opposing second face, the package substrate comprising a conductive trace in a dielectric material, a conductive structure at least partially surrounding the conductive trace and separated from the conductive trace by the dielectric material; and an integrated circuit (IC) die attached to the first face of the package substrate and coupled to the conductive trace by a conductive pathway through the package substrate.
Cemil Geyik, Zhiguo Qian, Kristof Kuwawi Darmawikarta, Zhichao Zhang, Kemal Aygun
Filed: 23 Jun 22
Utility
Single Lithography Methods for Interconnect Architectures
28 Dec 23
Various embodiments disclosed relate to a semiconductor assembly interconnect structure.
Yi Yang, Suddhasattwa Nad, Ali Lehaf, Jason Steill
Filed: 22 Jun 22