11728 patents
Page 7 of 587
Utility
Detecting Laser-injected Faults
4 Jan 24
An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander.
Minki Cho, Daniel Nemiroff, Carlos Tokunaga, James W. Tschanz, Kah Meng Yeem, Yaxin Shui
Filed: 1 Jul 22
Utility
Methods and Apparatus for Team Classification In Sports Analysis
4 Jan 24
An example apparatus includes processor circuitry to extract features from image data obtained from a plurality of cameras, the extraction of features performed using a plurality of sequential neural network layers; in response to each of the plurality of sequential neural network layer extracting the features, identify the extracted features in a torso region of the image data via a plurality of attention modules; estimate body landmarks from image data to localize an area; generate an upper heatmap mask based on a geometric center of the image data; calculate a loss function for the image data based on a cross-entropy loss, a pixel-wise loss, and a triplet loss determined from the extracted features and the generated heatmap mask; select lowest correlated classes based on calculated correlations between pairs of a plurality of classes; and calculate voting scores for groups associated with the lowest correlated classes.
Chenning Liu, Qiang Li, Wenlong Li, Yikai Fang, Hang Zheng, Jiansheng Chen
Filed: 23 Sep 21
Utility
Substrates with Nitrided Glass Cores
4 Jan 24
Substrates with nitrided glass cores, and methods of forming the same, are described herein.
Suddhasattwa Nad, Darko Grujicic, Rengarajan Shanmugam
Filed: 2 Jul 22
Utility
Voltage Contrast Scan Area on a Wafer
4 Jan 24
Embodiments described herein may be related to apparatuses, systems, processes, and/or techniques for identifying device defects on a wafer substrate using voltage contrast techniques and electronic beam scans by scanning an area on a portion of the wafer that includes ends of a plurality of traces that extend from the scan area respectively to blocks on the wafer that include devices to be tested.
Xiao WEN, Dipto THAKURTA, Sairam SUBRAMANIAN
Filed: 30 Jun 22
Utility
Layer Selection for Routing High-speed Signals In Substrates
4 Jan 24
A substrate comprising a core structure between a first metallization stack and a second metallization stack.
Arghya Sain, Sujit Sharan, Hoai V. Le, Jianyong Xie
Filed: 1 Jul 22
Utility
Package Heaters for Cold Temperature Operation and Method
4 Jan 24
A semiconductor package comprises two or more dies including at least one integrated circuit.
Ganesh Kondapuram, Chetan Rawal, Kevin Connolly, Robert Anderson
Filed: 30 Jun 22
Utility
Alignment Via-pad and Via-plane Structures
4 Jan 24
Disclosed herein are via-trace-via structures with improved alignment, and related devices and methods.
Veronica Aleman Strong, Aleksandar Aleksov
Filed: 1 Jul 22
Utility
Edge Delamination and Crack Prevention Methods for Sinx and Ti-cu Enabled Packages
4 Jan 24
Embodiments disclosed herein include package substrates and methods of forming such substrates.
Suddhasattawa NAD, Rahul N. MANEPALLI, Gang DUAN, Srinivas V. PIETAMBARAM, Yi YANG, Marcel WALL, Darko GRUJICIC, Haobo CHEN, Aaron GARELICK
Filed: 29 Jun 22
Utility
Build Up Material Architecture for Microelectronic Package Device
4 Jan 24
Microelectronic integrated circuit package structures include a first layer over a substrate, the first layer having a matrix material and a filler material within the matrix material.
Jieying Kong, Peumie Abeyratne Kuragama, Ala Omer, Ao Wang, Dilan Seneviratne
Filed: 1 Jul 22
Utility
Methods and Apparatus to Adhere a Dielectric to a Nonconductive Layer In Circuit Devices
4 Jan 24
Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices.
Kristof Darmawikarta, Srinivas Pietambaram, Benjamin Duong, Haobo Chen
Filed: 30 Jun 22
Utility
Substrate Having One or More Electrical Interconnects
4 Jan 24
An electronic device may include an integrated circuit, for instance a semiconductor die.
Suddhasattwa Nad, Steve Cho, Marcel Arlan Wall, Onur Ozkan, Ali Lehaf, Yi Yang, Jason Scott Steill, Gang Duan, Brandon C. Marin, Jeremy D. Ecton, Srinivas Venkata Ramanuja Pietambaram, Haifa Hariri, Bai Nie, Hiroki Tanaka, Kyle Mcelhinny, Jason Gamba, Venkata Rajesh Saranam, Kristof Darmawikarta, Haobo Chen
Filed: 30 Jun 22
Utility
Low Insertion Loss Coaxial Through-hole for Highspeed Input-ouput
4 Jan 24
An electronic device includes a substrate including a core layer having a first surface and a second surface opposite the first surface, and at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface.
Kristof Darmawikarta, Kemal Aygun, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Zhiguo Qian, Jiwei Sun
Filed: 29 Jun 22
Utility
Gate-all-around Transistor Circuit Modification Using Direct Contact And/or Access Probe Points
4 Jan 24
Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit.
Richard H. Livengood, Muhammad Usman Raza, Waqas Ali, Tahir Malik, Shida Tan, Martin Von Haartman, Mauro Kobrinsky, Amir Raveh, Clifford J. Engle
Filed: 1 Jul 22
Utility
Pocketed Copper In First Layer Interconnect and Method
4 Jan 24
A substrate package comprises a substrate comprised of buildup layers.
Suddhasattwa Nad, Jeremy D. Ecton, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jason Steill, Yi Yang, Marcel Arlan Wall
Filed: 1 Jul 22
Utility
Barrier for Minimal Underfill Keep-out Zones
4 Jan 24
An integrated circuit (IC) device package substrate comprises a plurality of first interconnect features to couple to a first IC die, a plurality of second interconnect features to couple to a second IC die, and one or more barrier features on a surface of the substrate.
Xavier F. Brun, Jonas G. Croissant
Filed: 1 Jul 22
Utility
Silicide and Silicon Nitride Layers Between a Dielectric and Copper
4 Jan 24
Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric.
Suddhasattwa NAD, Kristof DARMAWIKARTA, Srinivas V. PIETAMBARAM, Tarek A. IBRAHIM, Rahul N. MANEPALLI, Darko GRUJICIC, Marcel WALL, Yi YANG
Filed: 29 Jun 22
Utility
Interconnect Bridge with Similar Channel Lengths
4 Jan 24
An electronic device may include an interconnect bridge.
Lijiang Wang, Naren Sreenivas Viswanathan, Sujit Sharan, Jiwei Sun
Filed: 29 Jun 22
Utility
Sinx Based Surface Finish Architecture
4 Jan 24
Disclosed herein are microelectronics package architectures utilizing SiNx based surface finishes and methods of manufacturing the same.
Suddhasattwa Nad, Jason Steill, Yi Yang, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Marcel Arlan Wall, Gang Duan, Jeremy D. Ecton
Filed: 30 Jun 22
Utility
Integrated Circuit Package with Multi-layered Metallization Lines
4 Jan 24
IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition.
Jeremy Ecton, Aleksandar Aleksov, Kristof Darmawikarta, Robert A. May, Brandon Marin, Benjamin Duong, Suddhasattwa Nad, Hsin-Wei Wang, Leonel Arana, Darko Grujicic
Filed: 1 Jul 22
Utility
Substrates Having Adhesion Promotor Layers and Related Methods
4 Jan 24
Substrate assemblies having adhesion promotor layers and related methods are disclosed.
Yi Yang, Srinivas Pietambaram, Darko Grujicic, Marcel Wall, Suddhasattwa Nad, Ala Omer, Brian P. Balch, Wei Wei
Filed: 30 Jun 22