11728 patents
Page 5 of 587
Utility
Reconfigurable Side-channel Resistant Double-throughput Aes Accelerator
4 Jan 24
In one example an apparatus comprises a first input node to receive a first plaintext input, a second input node to receive a random mask, an advanced encryption standard (AES) engine configurable to operate in one of a first mode in which the random mask is added to the first plaintext input during one or more computations performed by the AES engine, or second mode in which the random mask is not added to the first plaintext input during one or more computations performed by the AES engine.
Raghavan Kumar, Vikram B. Suresh, Sanu K. Mathew
Filed: 30 Jun 22
Utility
Data Synchronization Techniques for a Hybrid Hardware Accelerator and Programmable Processing Array Architecture
4 Jan 24
Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator.
Kannan Rajamani, Kameran Azadet, Kevin Kinney, Thomas Smith, Zoran Zivkovic
Filed: 29 Jun 22
Utility
Multi-storage Element Single-transistor Crosspoint Memory Systems at Low Temperatures
4 Jan 24
Bits are stored in an array with multiple storage elements sharing a single access transistor and a storage line coupled to the transistor.
Abhishek Anil Sharma, Wilfred Gomes, Anand Murthy, Sagar Suthram, Tahir Ghani
Filed: 1 Jul 22
Utility
Scaled Gain Cell Enhanced at Low Temperatures
4 Jan 24
Bits are stored in cells having two transistors between two parallel bitlines.
Abhishek Anil Sharma, Sagar Suthram, Wilfred Gomes, Anand Murthy, Tahir Ghani
Filed: 1 Jul 22
Utility
Stacked Sram with Shared Wordline Connection
4 Jan 24
Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area.
Abhishek Anil Sharma, Wilfred Gomes, Tahir Ghani, Anand Murthy, Rajabali Koduri, Clifford Ong, Sagar Suthram
Filed: 1 Jul 22
Utility
Memory Arrays with Backside Components and Angled Transistors
4 Jan 24
Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein.
Abhishek A. Sharma, Sagar Suthram, Tahir Ghani, Anand S. Murthy, Cory E. Weber, Rishabh Mehandru, Wilfred Gomes, Pushkar Sharad Ranade
Filed: 30 May 23
Utility
Three-dimensional Dynamic Random Access Memory with Stacked Semiconductor Structures
4 Jan 24
Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory.
Abhishek Sharma, Tahir Ghani, Anand Murthy, Wilfred Gomes, Sagar Suthram
Filed: 1 Jul 22
Utility
Back-end-of-line 2D Memory Cell
4 Jan 24
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell.
Chia-Ching LIN, Shriram SHIVARAMAN, Kevin P. O'BRIEN, Ashish Verma PENUMATCHA, Chelsey DOROW, Kirby MAXEY, Carl H. NAYLOR, Sudarat LEE, Uygar E. AVCI, Sou-Chi CHANG
Filed: 30 Jun 22
Utility
Single Patterning Cylindrical Transistor and Capacitor Dynamic Random Access Memory
4 Jan 24
Integrated circuit dies, systems, and techniques are described herein related to one transistor-one capacitor dynamic random access memory.
Abhishek Sharma, Tahir Ghani, Wilfred Gomes, Anand Murthy
Filed: 1 Jul 22
Utility
Backside Reveal for Layered Multi-capacitor Single Transistor Memory Systems
4 Jan 24
Bits are stored in an array with multiple capacitors sharing a single access transistor and a common plate coupled to the transistor.
Abhishek Anil Sharma, Anand Murthy, Wilfred Gomes, Tahir Ghani
Filed: 1 Jul 22
Utility
Programmable Capacitor Memory Arrays with Stacked Access Transistors
4 Jan 24
Bits are stored in an array with multiple capacitors per access transistor.
Abhishek Anil Sharma, Tahir Ghani, Anand Murthy, Wilfred Gomes
Filed: 1 Jul 22
Utility
One-dimensional Overlay Marks
4 Jan 24
Embodiments disclosed herein include semiconductor die with overlay marks, electronic devices that include semiconductor dies with overlay marks, and methods of measuring overlay.
William Blanton, Deepak Selvanathan, Shakul Tandon, Martin N. Weiss
Filed: 30 Jun 22
Utility
Reducing Instrumentation Code Bloat and Performance Overheads Using a Runtime Call Instruction
4 Jan 24
Techniques for an instruction for a Runtime Call operation are described.
Michael LeMay, Dan Baum, Joseph Cihula, Joao Batista Correa Gomes Moreira, Anjo Lucas Vahldiek-Oberwagner, Scott Constable, Andreas Kleen, Konrad Lai, Henrique de Medeiros Kawakami, David M. Durham
Filed: 29 Jun 22
Utility
Instructions and Support for Horizontal Reductions
4 Jan 24
Techniques for performing horizontal reductions are described.
Menachem ADELMAN, Amit GRADSTEIN, Regev SHEMY, Chitra NATARAJAN, Leonardo BORGES, Chytra SHIVASWAMY, Igor ERMOLAEV, Michael ESPIG, Or BEIT AHARON, Jeff WIEDEMEIER
Filed: 2 Jul 22
Utility
Scalable Anonymized Defect Scanning of Components In Deployed Computing Systems
4 Jan 24
Managing scan detection of a component in a computing system includes detecting a scan interrupt, reading a scan register of the component, the scan register including a hashed identifier (ID) of the component; getting material vintage information of the component based at least in part on the hashed ID; and initiating a scan of the component based at least in part on the material vintage information to detect any defects in the component.
Rajesh Poornachandran, Kaushik Balasubramanian, Karan Puttannaiah
Filed: 29 Jun 22
Utility
Optimized Prioritization of Memory Accesses
4 Jan 24
Embodiments described herein may include apparatus, systems, techniques, or processes that are directed prioritizing memory requests from core processors such that some memory transaction requests receive a higher priority than other memory transaction requests.
Sai Prashanth Muralidhara, Narasimha Sridhar Srirangam, Rawan Abdel Khalek, Yedidya Hilewitz, Daniel Liu, Sharada Venkateswaran, Wolf Witt, Nishant Singh
Filed: 30 Jun 22
Utility
Accelerating Neural Networks with Low Precision-based Multiplication and Exploiting Sparsity In Higher Order Bits
4 Jan 24
An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed.
Avishaii Abuhatzera, Om Ji Omer, Ritwika Chowdhury, Lance Hacking
Filed: 18 Apr 23
Utility
Multiple Channel Direct Access Memory-based Configuration System
4 Jan 24
A system including a host device and an integrated circuit.
Gary Brian Wallichs, Andrew Martyn Draper, Kye Howe Wong, Kalen Brunham, Jeffrey Edward Erickson
Filed: 1 Jul 22
Utility
Techniques For Controlling Access To Provisioning Integrated Circuits
4 Jan 24
An integrated circuit includes a cryptographic engine that generates a cryptographic version of a password, a secure storage area, and a security controller circuit that stores an enable bit and at least a portion of the cryptographic version of the password in the secure storage area to enable a security feature.
Michael Neve De Mevergnies
Filed: 18 Sep 23
Utility
Providing Configurable Security for Intellectual Property Circuits of a Processor
4 Jan 24
In one embodiment, a method includes: receiving, in a replica circuit associated with a first intellectual property (IP) circuit of a system on chip (SoC), a security policy; receiving, in the replica circuit, a test data register access message to identify an access to a first test data register of the first IP circuit; and preventing the access to the first test data register based at least in part on the security policy.
Ratheesh Thekke Veetil, Gauri Shankar Singh
Filed: 29 Jun 22