10908 patents
Page 24 of 546
Utility
Method for forming embedded grounding planes on interconnect layers
17 Oct 23
Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces.
Brandon C. Marin, Kristof Darmawikarta, Roy Dittler, Jeremy Ecton, Darko Grujicic
Filed: 10 Apr 19
Utility
Microelectronic assemblies including a thermal interface material
17 Oct 23
Microelectronic assemblies, and related devices and methods, are disclosed herein.
Peng Li, Sergio Antonio Chan Arguedas, Yongmei Liu, Deepak Goyal, Ken Hackenberg
Filed: 27 Jun 18
Utility
cueuiebibil83p7cp4quj4deo56etirx7austqh12b926fpc
17 Oct 23
Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures.
Sairam Subramanian, Walid M. Hafez
Filed: 27 Dec 21
Utility
qnb90gx063iecqntu7262uz2xnq2igxdlhhb
17 Oct 23
Electrical interconnect bridge technology is disclosed.
Srinivas V. Pietambaram, Rahul N. Manepalli
Filed: 17 Jul 20
Utility
mzat6nkrn5uceif977k0laz7e2
17 Oct 23
Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods.
Manish Dubey, Omkar G. Karhade, Nitin A. Deshpande, Jinhe Liu, Sairam Agraharam, Mohit Bhatia, Edvin Cetegen
Filed: 16 Jun 20
Utility
7thzvyvuibd8vit22d5fq5odhrotf79tfyttyc8
17 Oct 23
Microelectronic assemblies, and related devices and methods, are disclosed herein.
Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
Filed: 8 Apr 22
Utility
5jjpq83 5zfbdyofe5qfbb9n0rnko4s64jmja6
17 Oct 23
Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices.
Nicholas A. Thomson, Kalyan C. Kolluru, Adam Clay Faust, Frank Patrick O'Mahony, Ayan Kar, Rui Ma
Filed: 15 Nov 21
Utility
to3ckypkukk0juswbde250mwd48glmka1ig 9gp8b
17 Oct 23
Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor.
Sudipto Naskar, Manish Chandhok, Abhishek A. Sharma, Roman Caudillo, Scott B. Clendenning, Cheyun Lin
Filed: 19 Jan 22
Utility
69fzoril3s9tg9lh7pbev8nk0c3651k558zzht89zlqd4fv0u34thq
17 Oct 23
Embodiments disclosed herein include semiconductor devices and methods of forming such devices.
Rahul Ramaswamy, Walid M. Hafez, Tanuj Trivedi, Jeong Dong Kim, Ting Chang, Babak Fallahazad, Hsu-Yu Chang, Nidhi Nidhi
Filed: 13 Dec 19
Utility
yqm725za0hv0gtwu5splnku2g05m1zi5nb49b
17 Oct 23
Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device.
Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
Filed: 6 Apr 22
Utility
6jftpmfbix7ix lsrtbp
17 Oct 23
Various embodiments provide a voltage regulator circuit including two or more discontinuous conduction mode (DCM) phases coupled to an output node and coupled in parallel with one another.
Juan Munoz Constantine, Alexander Lyakhov
Filed: 10 Mar 21
Utility
a3qo14owbdkg8zc31qbgt9fzq43zf0madr g15
17 Oct 23
A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization.
Steven Hsu, Amit Agarwal, Simeon Realov, Ram Krishnamurthy
Filed: 26 Dec 19
Utility
wn1y1k5xx2i0jf5huf0l9nssi9oxmnhnkpox2l913aglxtjouiyvixpph
17 Oct 23
Some demonstrative embodiments include devices, systems and/or methods of simultaneously communicating with a group of wireless communication devices.
Michelle X. Gong, Robert J. Stacey
Filed: 1 Mar 21
Utility
50fu2w8j1vjefskcja7d49rzy 03whasoochq9x8xba
17 Oct 23
Polynomial multiplication for side-channel protection in cryptography is described.
Santosh Ghosh, Manoj Sastry
Filed: 17 Sep 21
Utility
pa4ab4qi2cs8pyh7s1xjpj6hjkaikfnuvgrr8oielz4v4zbqdt48899uo2
17 Oct 23
A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive nth root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.
Santosh Ghosh, Andrew H. Reinders, Manoj Sastry
Filed: 21 Mar 22
Utility
bhgdfjs5nlvr2h5u62oghskzh8ftfxqwp6wv b8u6zk7dyewl4zi
17 Oct 23
Systems and methods for dynamic compute orchestration include receiving, at a network node of an information centric network, a first interest packet comprising a name field indicating a named function and one or more constraints specifying compute requirements for a computing node to execute the named function, the first interest packet received from a client node.
Nageen Himayat, Srikathyayani Srikanteswara, Krishna Bhuyan, Daojing Guo, Rustam Pirmagomedov, Gabriel Arrobo Vidal, Yi Zhang, Dmitri Moltchanov
Filed: 2 Jul 20
Utility
gj8wtp89hfs8p6qx6op6z5ua r7a1gn93yt1lqp5528gionm2j
17 Oct 23
Examples relate to a transmission apparatus, transmission device, transmission method and computer program for a source device, and to a reception apparatus, reception device, reception method and computer program for a destination device.
Naveed Alam, Dhruba Deka, Ravindra Singh
Filed: 22 Mar 21
Utility
mjnqx4kecvrc0j0s69mzc2snhjwvy7a8m6lkzfnaamdsig9vs5trow3yyxo
17 Oct 23
Technologies for aligning network flows to processing resources include a computing device having multiple processing nodes, a network switch, and a network controller operating in a software-defined network.
Iosif Gasparakis, Brian P. Johnson, Patrick G. Kutch
Filed: 24 Aug 20
Utility
a22kkyt uj5wfdry9v25zl42vc5uz3r13rkcga8ax2cmef
17 Oct 23
The disclosure provides some embodiments for securing long training field (LTF) sequence.
Qinghua Li, Jonathan Segev, Benny Abramovsky, Danny Alexander, Xiaogang Chen, Chittabrata Ghosh, Feng Jiang, Ido Ouzieli, Robert Stacey
Filed: 16 May 22
Utility
bz9wsnu1aq h4s2txib9ic5iywd77f
17 Oct 23
In one example a prover device comprises one or more processors, a computer-readable memory, and signature logic to store a first cryptographic representation of a first trust relationship between the prover device and a verifier device, the first cryptographic representation based on a pair of asymmetric hash-based multi-time signature keys, receive an attestation request message from the verifier device, the attestation request message comprising attestation data for the verifier device and a hash-based signature generated by the verifier device, and in response to the attestation request message, to verify the attestation data, verify the hash-based signature generated by the verifier device using a public key associated with the verifier device, generate an attestation reply message using a hash-based multi-time private signature key and send the attestation reply message to the verifier device.
Xiruo Liu, Rafael Misoczki, Santosh Ghosh, Manoj Sastry
Filed: 11 Feb 22