Intel (INTC) USPTO patentsUtility grant

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Fine-grained pipelining using index space mapping

1 Aug 23

A method for computing includes defining a processing pipeline, including at least a first stage in which producer processors compute and output data to respective locations in a buffer and a second processing stage in which one or more consumer processors read the data from the buffer and apply a computational task to the data read from the buffer.

Tzachi Cohen, Michael Zuckerman, Doron Singer, Ron Shalev, Amos Goldman

Filed: 15 Feb 21

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Content presentation with enhanced closed caption and/or skip back

1 Aug 23

Apparatuses, methods and storage medium associated with content consumption are disclosed herein.

Johannes P. Schmidt

Filed: 29 Sep 20

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1 Aug 23

Examples described herein relate to a network interface controller apparatus, that includes a processor component comprising at least one processor to generate remote memory access communications to access a first group of one or more namespaces; storage interface circuitry to generate remote memory access communications to access a second group of one or more namespaces; and a storage configuration circuitry with a device interface that is accessible through a user space driver, the storage configuration circuitry to set the first and second group of one or more namespaces.

Yadong Li, Jose Niell, Kiel Boyle

Filed: 24 Sep 20

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1 Aug 23

In one embodiment, an apparatus comprises a storage device and a processor.

Luis Carlos Maria Remis, Vishakha Gupta, Christina R. Strong, Philip R. Lantz

Filed: 29 Jun 21

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1 Aug 23

Systems, methods, and apparatuses relating to a matrix operations accelerator are described.

Amit Gradstein, Simon Rubanovich, Sagi Meller, Saeed Kharouf, Gavri Berger, Zeev Sperber, Jose Yallouz, Ron Schneider

Filed: 28 Dec 19

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1 Aug 23

Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules.

Chee Hak Teh, Ankireddy Nalamalpu, Md Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang

Filed: 2 Aug 21

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1 Aug 23

Systems, apparatuses and methods may provide for replacing floating point matrix multiplication operations with an approximation algorithm or computation in applications that involve sparse codes and neural networks.

Gautham Chinya, Shihao Ji, Arnab Paul

Filed: 17 Dec 21

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1 Aug 23

An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed.

Avishaii Abuhatzera, Om Ji Omer, Ritwika Chowdhury, Lance Hacking

Filed: 23 Jun 20

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1 Aug 23

An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass.

Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach

Filed: 24 Apr 19

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1 Aug 23

Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault.

Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu

Filed: 3 Mar 22

Utility

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1 Aug 23

Apparatus and methods for extraction and calculation of multi-person performance metrics in a three-dimensional space.

Nelson Leung, Jonathan K. Lee, Bridget L. Williams, Sameer Sheorey, Amery Cong, Mehrnaz Khodam Hazrati, Sabar Mourad Souag, Adam Marek, Pawel Pieniazek, Bogna Bylicka, Jakub Powierza, Anna Banaszczyk-fiszer

Filed: 26 Jun 20

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1 Aug 23

An Autonomous Vehicle (AV) system, including: a tracking subsystem configured to detect and track relative positioning of another vehicle that is behind or lateral to an AV configured to comply with a safety driving model, and to check a safety driving model compliance status of the other vehicle; and a risk reduction subsystem configured to plan, based on the safety driving model compliance status of the other vehicle, an AV action, wherein if the safety driving model compliance status of the other vehicle is unknown or is known to be non-compliant, the AV action is administration of a safety driving model compliance test to the other vehicle, or is a maneuver by the AV to reduce risk of collision with a leading vehicle positioned in front of the AV.

Javier Turek, Ignacio J. Alvarez, Maria Soledad Elli, Javier Felip Leon, David I. Gonzalez Aguirre

Filed: 28 Dec 19

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1 Aug 23

Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die.

Georgios Dogiamis, Aleksandar Aleksov, Adel A. Elsherbini, Henning Braunisch, Johanna M. Swan, Telesphor Kamgaing

Filed: 29 Apr 19

Utility

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1 Aug 23

An integrated circuit package is disclosed.

Mathew J. Manusharow, Jonathan Rosenfeld

Filed: 17 Dec 21

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1 Aug 23

Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described.

Rohan K. Bambery, Walid M. Hafez, Mong-Kai Wu

Filed: 21 Feb 22

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1 Aug 23

Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described.

Leonard P. Guler, Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar

Filed: 29 Apr 22

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1 Aug 23

A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Mark Armstrong, Biswajeet Guha, Jun Sung Kang, Bruce Beattie, Tahir Ghani

Filed: 29 Oct 21

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1 Aug 23

Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned.

Nidhi Nidhi, Marko Radosavljevic, Sansaptak Dasgupta, Yang Cao, Han Wui Then, Johann Christian Rode, Rahul Ramaswamy, Walid M. Hafez, Paul B. Fischer

Filed: 22 Apr 19

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1 Aug 23

A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed.

Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Kevin Lin, Paul Fischer

Filed: 28 Sep 17

Utility

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1 Aug 23

Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed.

Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then

Filed: 15 Nov 21