135 patents
Page 7 of 7
Utility
Formal verification using microtransactions
23 Dec 19
Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions.
Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Bryan D. Bowyer, Andres R. Takach, Peter P. Gutberlet, Gagandeep Singh, Maheshinder Goyal
Filed: 9 Nov 17
Utility
Test application time reduction using capture-per-cycle test points
16 Dec 19
Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time.
Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
Filed: 29 Jan 18
Utility
Timing-aware test generation and fault simulation
16 Dec 19
Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects.
Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
Filed: 30 Jul 17
Utility
Target capture and replay in emulation
9 Dec 19
An emulation process is performed with an emulator coupled to one or more targets.
Krishnamurthy Suresh, Satish Kumar Agarwal, Sanjay Gupta, Charles W. Selvidge
Filed: 3 Aug 17
Utility
Generating root cause candidates for yield analysis
2 Dec 19
Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis.
Robert Brady Benware, Wu-Tung Cheng, Christopher Schuermyer, Jonathan J. Muirhead, Chen-Yi Chang
Filed: 11 Sep 16
Utility
Context-aware pattern matching for layout processing
2 Dec 19
Aspects of the disclosed technology relate to techniques of context-aware pattern matching and processing.
Sherif Hany Riad Mohammed Mousa, Jonathan James Muirhead, Alex Joseph Pearson, William Matthew Hogan
Filed: 16 Jan 18
Utility
Dynamic model generation for lithographic simulation
2 Dec 19
Disclosed are techniques for processing layout designs based on dynamically-generated lithographic models.
Michael Christopher Lam, Germain Louis Fenger, Ananthan Raghunathan, Konstantinos G. Adam, Christopher Heinz Clifford
Filed: 2 Oct 17
Utility
Data streaming for testing identical circuit blocks
11 Nov 19
Various aspects of the disclosed technology relate to streaming data for testing identical circuit blocks in a circuit.
Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
Filed: 18 Mar 18
Utility
Data generation for streaming networks in circuits
11 Nov 19
Various aspects of the disclosed technology relate to generating streaming data and configuration data for streaming networks in circuits.
Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
Filed: 18 Mar 18
Utility
Simulation-assisted wafer rework determination
14 Oct 19
Aspects of the disclosed technology relate to techniques for using hotspot simulation to make wafer rework decisions.
John L. Sturtevant, Shumay Dou Shang, Konstantinos G. Adam
Filed: 3 Oct 17
Utility
Social electronic design automation
14 Oct 19
This application discloses web or cloud-based electronic design automation tools, which can incorporate functionality to enable collaborative and/or social interaction among multiple different users of the electronic design automation tools.
Adam Cabler, Darrell A. Teegarden
Filed: 29 Jan 14
Utility
Manufacture of non-rectilinear features
14 Oct 19
Methods and apparatus are disclosed for symbolic methods using algebraic geometry (e.g., based on a Gröbner basis of tangent space polynomials of parametric curves).
Sandeep Koranne
Filed: 19 Jan 16
Utility
Test point insertion for low test pattern counts
14 Oct 19
Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques.
Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer, Justyna Zawada
Filed: 14 Oct 15
Utility
Take rate determination
7 Oct 19
This application discloses a system implementing tools and mechanisms to receive a target rate for each option available for inclusion in a harness family, determine combination take rates for different combinations of the options based on the target rates for the options, and utilize the combination take rates and the combinations of the options to identify one or more wire harnesses, each including a different set of the options, in the harness family.
Stephen Bold
Filed: 22 Dec 14
Utility
Test capability-based printed circuit board assembly design
30 Sep 19
This application discloses a computing system implementing a schematic capture tool to utilize physical test capabilities of a manufacturer of a printed circuit board assembly during generation of a logical design for the printed circuit board assembly.
Mark Laing
Filed: 29 Jan 17