135 patents
Page 5 of 7
Utility
Concurrent testbench and software driven verification
25 May 20
A verification system comprises: a reconfigurable hardware modeling device programmed to implement a hardware model of a circuit design; a first computing unit configured to execute a first software program; and a second computing unit configured to execute a testbench model of a second software program.
Debdutta Bhattacharya, Ayub Akbar Khan, Charles W. Selvidge
Filed: 1 Apr 18
Utility
Bandwidth test in networking System-on-Chip verification
25 May 20
Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification.
Suresh Krishnamurthy, Deepak Kumar Garg, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland, III, Ronald James Squiers, Charles W. Selvidge
Filed: 23 Oct 17
Utility
Testbench restoration based on capture and replay
25 May 20
Messages transmitted from an emulator to a testbench of a part of the testbench are recorded from a starting point of an emulation operation to a checkpoint of the emulation operation.
Suresh Krishnamurthy, Ruchir Prakash, Jeffrey W. Evans, Deepak Kumar Garg
Filed: 27 Dec 15
Utility
Pattern correction in multiple patterning steps
18 May 20
This application discloses a computing system to simulate a wafer image based on a mandrel mask and a block mask to be utilized to print a final wafer image on a substrate.
James C. Word, Shady AbdelWahed
Filed: 19 Jan 16
Utility
Inter-cell bridge defect diagnosis
18 May 20
Failing test pattern simulations are performed to determine initial defect suspects based on injecting faults to defect candidate sites which are derived based on test responses.
Huaxing Tang, Manish Sharma, Szczepan Urban
Filed: 6 May 18
Utility
Slack time recycling
18 May 20
This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware.
Brian Etscheid, Terry Goode, Spencer Saunders
Filed: 15 Jan 18
Utility
Latency test in networking system-on-chip verification
18 May 20
Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification.
Suresh Krishnamurthy, Deepak Kumar Garg, Sudhanshu Jayaswal, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland, III, Ronald James Squiers, Abhijit Das, Charles W. Selvidge
Filed: 23 Oct 17
Utility
Part number consolidation in printed circuit board assembly design
18 May 20
This application discloses a computing system implementing part number consolidation functionality can determine part numbers available for assignment to components represented in a printed circuit board assembly design based on electrical or physical characteristics associated with the components.
Sami Aarras, Mark Laing, Jeremy Schitter
Filed: 31 May 18
Utility
Wafer map pattern detection based on supervised machine learning
18 May 20
Various aspects of the disclosed technology relate to training and applying a machine learning model for defect pattern detection.
Patrick Jon Milligan
Filed: 29 Apr 18
Utility
Properties in electronic design automation
4 May 20
One or more properties can be associated with a design object in a microdevice design.
Fedor G. Pikus, Phillip A. Brooks, Gary S. Myron
Filed: 8 Oct 07
Utility
Glitch detection at clock domain crossing
27 Apr 20
This application discloses a computing system to perform one or more static checks on clock domain crossings in a circuit design to detect combinational logic configured to generate output signals having glitches that cross clock domains in a circuit design.
Sulabh Kumar Khare, Ashish Hari
Filed: 30 Jan 18
Utility
Flow control in networking system-on-chip verification
20 Apr 20
A system for verifying networking system-on-chip designs comprises a reconfigurable hardware modeling device programmed to implement circuitry hardware models and a traffic generation device communicating with the reconfigurable hardware modeling device.
Suresh Krishnamurthy, Deepak Kumar Garg, Ankit Garg, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland, III, Ronald James Squiers
Filed: 23 Oct 17
Utility
Prototype wiring synthesis
20 Apr 20
This application discloses a computing system to receive a specification of prototype wiring corresponding to a signal in a logical design of a wire harness, locate a section of a vehicle to include a portion of the wire harness corresponding to the signal in the logical design, and insert the prototype wiring into a physical design of the wire harness corresponding to the located section of the vehicle.
Simon Holdsworth, Rory Harrington, David Barnes
Filed: 30 Jan 18
Utility
Power mode-based operational capability-aware code coverage
6 Apr 20
This application discloses a design verification tool implementing in a functional verification environment with a computing system, a hardware emulator, or a combination thereof.
Pankaj Kumar Dwivedi, Shweta Gulati
Filed: 30 Jan 18
Utility
Logic-driven layout verification
23 Mar 20
A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component.
Sridhar Srinivasan, Fedor G. Pikus, Patrick D. Gibson, Padmaja Susarla
Filed: 30 Jan 11
Utility
Circuit simulation waveform generation and display
23 Mar 20
Simulation waveforms representative of simulation progress are generated and outputted for display.
Amit Mehrotra, Francois Le Grix, Paul Estrada
Filed: 24 Mar 14
Utility
Power management with hardware virtualization
16 Mar 20
This application discloses a computing system that can enter into a low power mode, shut down all components except for memory, and exit from the low power mode and restore running programs where they left off before entering the low power mode.
Karl Büehler
Filed: 3 Jan 16
Utility
Cell-aware root cause deconvolution for defect diagnosis and yield analysis
16 Mar 20
Logic diagnosis is performed on failing reports of defective integrated circuits to derive a diagnosis report for each of the failing reports which comprise information of suspects.
Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Gaurav Veda
Filed: 25 Oct 18
Utility
Assertion statement check and debug
16 Mar 20
This application discloses a computing system to check and generate an assertion statement.
Moaz Magdy Mustafa, Mona Safar, Mohamed Dessouky
Filed: 27 Nov 16
Utility
Parasitic extraction based on compact representation of process calibration data
16 Mar 20
Aspects of the disclosed technology relate to techniques of parasitic extraction using compact representation of process calibration data.
Sandeep Koranne, Sridhar Srinivasan
Filed: 16 Jan 18