135 patents
Page 6 of 7
Utility
Vehicle localization with map-matched sensor measurements
9 Mar 20
This application discloses a computing system to implement vehicle localization in an assisted or automated driving system.
Ljubo Mercep, Matthias Pollach
Filed: 29 Jan 17
Utility
Removal of artificial resonances using boundary element method
9 Mar 20
This application discloses a computing system configured to crop a layout design for an electronic device implemented with a layered interconnect, place a termination structure corresponding to a resistive sheet or a set of resistive components on an artificial boundary corresponding to an edge in the cropped portion of the layout design, and generate an electrical model of a signaling net in the cropped portion of the layout design by generating mesh elements on a surface area of the cropped portion of the layout design including the termination structure and utilizing a field solver implementing a Boundary Element Method based analysis to solve integral forms of Maxwell's equations corresponding to the mesh elements.
Swagato Chakraborty, James Pingenot, Mosin Mondal
Filed: 19 Oct 17
Utility
Selective conditional stall for hardware-based circuit design verification
2 Mar 20
Various aspects of the present disclosed technology relate to techniques for selective conditional stall for speeding up hardware-based circuit verification.
Charles W. Selvidge, Ansuman Prusty, Vipul Kulshrestha, Kenneth W. Crouch, Matthew L. Dahl, Laurent Vuillemin
Filed: 29 Oct 18
Utility
Back-pressure in virtual machine interface
24 Feb 20
This application discloses a computing system having a virtual machine and a host program that communicate via a virtual interface.
Ankit Garg, John R. Stickley, Deepak Kumar Garg, Georges Antoun Elias Ghattas, Hanan Mohamed Sameh Tawfik, Abdallah Galal Yahya Khalil
Filed: 22 Jan 17
Utility
Interconnect reuse resolution with bump compensation in a package design
24 Feb 20
This application discloses a computing system to export route data and connectivity data from a layout design of a package device.
Frank Bader, John Medina
Filed: 27 Nov 16
Utility
System for processing messages of data stream
24 Feb 20
A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.
Kari Vierimaa
Filed: 28 Jun 17
Utility
Single simulation-based structure function mapping
24 Feb 20
A thermal transient response simulation is performed for a structure having a plurality of thermal model elements.
Byron Blackmore, Joseph Charles Proulx, Robin Bornoff, Andras Vass-Varnai
Filed: 23 Oct 17
Utility
Communication circuitry in an electronic control unit
17 Feb 20
This application discloses an electronic control unit coupled to a bus in a vehicle communication network.
Ahmed Hamed, Mona Safar, Ashraf Salem
Filed: 13 Mar 17
Utility
Map building with sensor measurements
10 Feb 20
This application discloses a computing system to implement map building in an assisted or automated driving system.
Ljubo Mercep, Matthias Pollach
Filed: 30 Jan 17
Utility
Controlling real time during embedded system development
3 Feb 20
Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system.
Lance S. P. Brooks, Darrell A. Teegarden
Filed: 2 Oct 16
Utility
Simultaneous multi-layer fill generation
3 Feb 20
Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer.
Eugene Anikin, Fedor G. Pikus, Laurence Grodd, David A. Abercrombie, John W. Stedman
Filed: 21 Nov 16
Utility
Resistor network reduction for full-chip simulation of current density
27 Jan 20
Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification.
Sridhar Srinivasan, Armen Asatryan, Patrick Gibson, Grigor Geoletsyan
Filed: 16 Jan 18
Utility
Full memory logical erase for circuit verification
27 Jan 20
A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to supply a sector status value for each memory sector of the memory which is changed to a value equal to the memory status value when a write operation is performed on the each memory sector of the memory; and third circuitry configured to supply, when a read operation is performed on a memory sector of the memory, a value stored in the memory sector as output of the read operation if the sector status value for the memory sector is equal to the memory status value or a predefined value as the output of the read operation in other situations.
Khaled Salah Mohamed, Hans Erich Multhaup, Robert John Bloor
Filed: 17 Sep 18
Utility
System, method, and computer program product for conditionally eliminating a memory read request
13 Jan 20
A system, method and computer program product are provided for conditionally eliminating a memory read request.
Nikhil Tripathi, Venky Ramachandran, Malay Haldar, Sumit Roy, Anmol Mathur, Abhishek Roy, Mohit Kumar
Filed: 22 Jun 17
Utility
Acceleration of voltage propagation based on local iteration
13 Jan 20
Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification.
Mark E. Hofmann, Sridhar Srinivasan, Gregory P. Hackney
Filed: 16 Aug 16
Utility
Reconfigurable scan network defect diagnosis
30 Dec 19
A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault.
Givargis Avareh Danialy, Martin Keim
Filed: 20 May 18
Utility
Event classification and object tracking
30 Dec 19
This application discloses a computing system to implement object tracking in an assisted or automated driving system of a vehicle.
Ljubo Mercep, Matthias Pollach
Filed: 29 Jan 17
Utility
Covergroup network analysis
30 Dec 19
This application discloses performing functional verification on a circuit design describing an electronic device and a computing system to determine occurrences of coverpoints and coverage crosses within a covergroup based on the results of the functional verification of the circuit design.
Mennatallah Amer
Filed: 30 Jan 18
Utility
Traffic shaping in networking system-on-chip verification
30 Dec 19
Traffic-shaping information is associated with ingress transaction-level messages by a traffic generation device.
Krishnamurthy Suresh, Deepak Kumar Garg, Sudhanshu Jayaswal, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland, III, Ronald James Squiers
Filed: 23 Oct 17
Utility
Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation
30 Dec 19
Low power very large scale integrated (VLSI) designs using a circuit failure in sequential cells as low voltage check for limit of operation of a design are provided.
Sanjay Pillay
Filed: 6 Oct 16