28912 patents
Page 11 of 1446
Utility
Semiconductor Device and Formation Method Thereof
11 Jan 24
A method of forming a semiconductor device includes forming a fin over a substrate, the fin comprising alternately stacking first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form spaces each between the second semiconductor layers, forming a gate dielectric layer wrapping around each of the second semiconductor layers, forming a fluorine-containing layer on the gate dielectric layer, performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer, removing the fluorine-containing layer, and forming a metal gate on the gate dielectric layer.
Hsin-Yi LEE, Shan-Mei LIAO, Kuo-Feng YU, Da-Yuan LEE, Weng CHANG, Chi On CHUI
Filed: 5 Jul 22
Utility
Semiconductor Package and Method
11 Jan 24
A semiconductor package including a thermally conductive bridge and a method of forming are provided.
Ming-Fa Chen
Filed: 7 Jul 22
Utility
Semiconductor Structure and Method for Forming the Same
11 Jan 24
A semiconductor structure is provided.
Jhon-Jhy LIAW
Filed: 8 Jul 22
Utility
Semiconductor Device Structure with Gate Stack and Method for Forming the Same
11 Jan 24
A method for forming a semiconductor device structure is provided.
Huan-Chieh SU, Chun-Yuan CHEN, Lin-Yu HUANG, Chih-Hao WANG
Filed: 5 Jul 22
Utility
Semiconductor Device and Method of Forming the Same
11 Jan 24
Provided are a semiconductor device and a method of forming the same.
Sheng-Feng Huang, Kam-Tou Sio, Jiann-Tyng Tzeng, Shang-Wei Fang, Chun-Yen Lin
Filed: 11 Jul 22
Utility
Image Sensor Having a Lateral Photodetector Structure
11 Jan 24
The present disclosure relates to an image sensor including a first semiconductor layer having a first doping type.
Kuo-Chin Huang, Tzu-Jui Wang
Filed: 5 Jul 22
Utility
Replacement Structures
11 Jan 24
Provided are devices with replacement structures and methods for fabricating such structures.
Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Chih-Han Li, Ming-Ching Chang, Chao-Cheng Chen
Filed: 11 Jul 22
Utility
High Voltage Resistor with High Voltage Junction Termination
11 Jan 24
High voltage semiconductor devices are described herein.
Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
Filed: 12 Jun 23
Utility
Ldmos Transistor and Method of Forming the Same
11 Jan 24
A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack.
Chun-Ching Wu, Po-Jen Wang
Filed: 21 Sep 23
Utility
Threshold Voltage Modulation by Gate Height Variation
11 Jan 24
Semiconductor devices and methods of forming the same are provided.
Ta-Chun Lin, Chih-Pin Tsao, Chih-Hao Chang
Filed: 30 Aug 22
Utility
Gate Isolation Wall for Semiconductor Device
11 Jan 24
The present disclosure describes a semiconductor device having an isolation structure.
Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
Filed: 22 Mar 23
Utility
Method and Structure for Diodes with Backside Contacts
11 Jan 24
A semiconductor structure includes a first semiconductor layer having an upper portion over a lower portion, a source/drain feature over the upper portion of the first semiconductor layer, a first contact structure under the lower portion of the first semiconductor layer and electrically connected to the lower portion of the first semiconductor layer.
Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
Filed: 9 Aug 23
Utility
Semiconductor Device
11 Jan 24
A device includes a channel layer, a gate structure, a first gate spacer, and a second gate spacer.
Cheng-Hsien WU
Filed: 21 Sep 23
Utility
Gate-top Dielectric Structure for Self-aligned Contact
11 Jan 24
Semiconductor structures and methods of forming the same are provided.
Ta-Chun Lin, Yi-Hsien Chen, Wen-Cheng Luo, Chung-Ting Li, Yi-Shien Mor, Chih-Hao Chang
Filed: 6 Jan 23
Utility
Semiconductor Chip
11 Jan 24
A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided.
Bo-Feng Young, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Yu Chang, Han-Jong Chia
Filed: 21 Sep 23
Utility
Gated Tri-state Inverter, and Method of Operating Same
11 Jan 24
A gated tri-state (G3S) inverter includes: first, second and third transistors of a first dopant type (D1 transistors) and first, second and third transistors of a second dopant type (D2 transistors) serially connected between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type; gate terminals of an alpha one of the noted D1 transistors and an alpha one of the noted D2 transistors being configured to receive an input signal; gate terminals of a beta one of the noted D1 transistors and a beta one of the noted D2 transistors being configured to receive a gating signal; a gate terminal of a gamma one of the noted D2 transistors being configured to receive an enable signal; and a gate terminal of a gamma one of the noted D1 transistors being configured to receive an enable_bar signal.
Tsung-Che LU, Chin-Ming FU, Chih-Hsien CHANG
Filed: 10 Aug 23
Utility
Semiconductor Structure and Manufacturing Method Thereof
11 Jan 24
A method includes forming a transistor on a front-side of a substrate, the transistor comprising a channel region, a gate structure surrounding the channel region, and source/drain regions on opposite sides of the gate structure; forming a front-side contact on a first one of the source/drain regions of the transistor, forming a back-side contact on a second one of the source/drain regions of the transistor; forming a back-side capacitor on the back-side contact.
Jhon Jhy LIAW
Filed: 6 Jul 22
Utility
Semiconductor Device with Backside Power Rail
11 Jan 24
A method of fabricating a semiconductor device includes providing a dummy structure including channel layers disposed over a frontside of a substrate, inner spacers disposed between adjacent channels of the channel layers and at lateral ends of the channel layers, and a gate structure interposing the plurality of channel layers.
Pei-Yu Wang, Yu-Xuan Huang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu
Filed: 22 Feb 23
Utility
Semiconductor Device and Method of Manufacturing the Same
11 Jan 24
A method of manufacturing a memory cell includes the following steps.
Chia-Yu Ling, Katherine H. CHIANG, Chung-Te Lin
Filed: 21 Sep 23
Utility
Dopant Concentration Boost in Epitaxially Formed Material
11 Jan 24
A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided.
Chih-Yu Ma, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee
Filed: 7 Aug 23