28912 patents
Page 12 of 1446
Utility
Memory Device and Method for Making Same
11 Jan 24
A memory device includes transistor structures and memory arc wall structures.
Yu-Wei Jiang, Hung-Chang Sun, Sheng-Chih Lai, Kuo-Chang Chiang, TsuChing Yang
Filed: 22 Sep 23
Utility
Metal Features of a Semiconductor Device and Methods for Forming the Same
11 Jan 24
A method is provided that includes depositing a catalyst layer along a surface of the opening and performing a selectivity enhancement process.
Kuan-Kan HU, Tsung-Kai CHIU, Wei-Yen WOON, Szuya LIAO, Ku-Feng YANG
Filed: 26 Jan 23
Utility
Semiconductor Device and Manufacturing Method Thereof
11 Jan 24
A semiconductor device includes a semiconductor substrate and an interconnection structure.
Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu BAO, Hengyuan Lee, Ying-Yu Chen
Filed: 22 Sep 23
Utility
Three-Dimensional Memory Device and Method
11 Jan 24
In an embodiment, a device includes a first gate structure over a substrate, the first gate structure including a first gate electrode over a first side of a first gate dielectric; a first electrode and a second electrode disposed over a second side of the first gate dielectric opposite the first side; a second gate structure disposed between the first electrode and the second electrode, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric at least laterally surrounding the second gate electrode; and a semiconductor film disposed between the first electrode and the second electrode and at least laterally surrounding the second gate structure, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.
Meng-Han Lin, Sai-Hooi Yeong, Chia-En Huang, Chi On Chui
Filed: 10 Jan 23
Utility
Memory Device and Method of Fabricating the Same
11 Jan 24
A memory device includes a substrate, a reference layer, a tunneling layer, a film stack, and a capping layer.
Po-Sheng Lu, Zhi-Ren Xiao, Nuo Xu, Zhiqiang Wu
Filed: 10 Jul 22
Utility
Ferroelectric Memory Device and Method of Forming the Same
11 Jan 24
A device includes a memory layer over a substrate; a first source/drain structure and a second source/drain structure on the memory layer, wherein the first source/drain structure and the second source drain structure each include a first source/drain layer on the memory layer; a second source/drain layer on the first source/drain layer, wherein the second source/drain layer is different from the first source/drain layer; and a metal layer on the second source/drain layer; and a channel region extending on the memory layer from the first source/drain layer of the first source/drain structure to the first source/drain layer of the second source/drain structure.
Meng-Han Lin, Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
Filed: 10 Jan 23
Utility
Memory Cell, Integrated Circuit, and Manufacturing Method of Memory Cell
11 Jan 24
Hengyuan Lee, Yu-Sheng Chen, Cheng-Chun Chang, Xinyu BAO
Filed: 7 Jul 22
Utility
Magnetic Tunnel Junction Devices
11 Jan 24
A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer.
Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih-Wei LU, Chung-Ju LEE
Filed: 25 Sep 23
Utility
Memory Cell, Integrated Circuit, and Manufacturing Method of Memory Cell
11 Jan 24
A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer.
Yu-Chao Lin, Tung-Ying Lee, Da-Ching Chiou
Filed: 21 Sep 23
Utility
CMP polishing head design for improving removal rate uniformity
9 Jan 24
An apparatus for performing chemical mechanical polish on a wafer includes a polishing head that includes a retaining ring.
Te-Chien Hou, Ching-Hong Jiang, Kuo-Yin Lin, Ming-Shiuan She, Shen-Nan Lee, Teng-Chun Tsai, Yung-Cheng Lu
Filed: 19 Dec 22
Utility
Pellicle and method of using the same
9 Jan 24
A pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle.
Chue San Yoo, Hsin-Chang Lee, Pei-Cheng Hsu, Yun-Yue Lin
Filed: 18 Oct 22
Utility
Polymer layer in semiconductor device and method of manufacture
9 Jan 24
A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer.
Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
Filed: 21 Sep 20
Utility
Inverted integrated circuit and method of forming the same
9 Jan 24
An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact.
Pochun Wang, Yu-Jung Chang, Hui-Zhong Zhuang, Ting-Wei Chiang
Filed: 13 Dec 22
Utility
Base layout cell
9 Jan 24
Systems, methods and devices are provided, which can include an engineering change order (ECO) base.
Shang-Hsuan Chiu, Chih-Liang Chen, Hui-Zhong Zhuang, Chi-Yu Lu, Kuang-Ching Chang
Filed: 27 Aug 21
Utility
Compensation word line driver
9 Jan 24
Memory systems are provided.
Chia-Hao Pao, Shih-Hao Lin, Kian-Long Lim
Filed: 20 May 22
Utility
Seed layer for ferroelectric memory device and manufacturing method thereof
9 Jan 24
A method includes: providing a bottom layer; forming a first transistor over a substrate; forming a bottom electrode over the transistor; depositing a first seed layer over the bottom electrode; performing a surface treatment on the first seed layer, wherein after the surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.
Chun-Chieh Lu, Sai-Hooi Yeong, Yu-Ming Lin
Filed: 30 Mar 22
Utility
Method and system of control of epitaxial growth
9 Jan 24
A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate.
Winnie Victoria Wei-Ning Chen, Andrew Joseph Kelly
Filed: 21 Feb 22
Utility
Integrated circuit component and package structure having the same
9 Jan 24
An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias.
Tzuan-Horng Liu, Chao-Hsiang Yang, Hsien-Wei Chen, Ming-Fa Chen
Filed: 22 Jul 22
Utility
Semiconductor package and manufacturing method thereof
9 Jan 24
A semiconductor package includes a redistribution structure, a plurality of semiconductor devices, and a plurality of heat dissipation films.
Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
Filed: 23 Jul 21
Utility
Heterogeneous dielectric bonding scheme
9 Jan 24
A method includes putting a first package component into contact with a second package component.
Chen-Hua Yu, Wen-Chih Chiou, Ku-Feng Yang, Ming-Tsu Chung
Filed: 6 Dec 21