1577 patents
Page 49 of 79
Utility
Semiconductor Device, Motor Control System, and Error Detection Method
28 Oct 20
According to semiconductor device includes a domain converter for converting a digitized resolver signal from a time-domain to a frequency-domain, a spectrum analyzer for analyzing a spectrum of the resolver signal converted to a frequency-domain by the domain converter, and an error detector for detecting an error related to the resolver signal based on an output signal from the spectrum analyzer.
Yutaka OSHIMA, Hisaaki WATANABE
Filed: 24 Mar 20
Utility
Electrode Device, Semiconductor Device, and Semiconductor System
28 Oct 20
The present invention provides an electrode device, semiconductor device and a semiconductor system capable of accuracy detecting an object to be detected.
Takuya MIZOKAMI, Masahiro ARAKI
Filed: 25 Mar 20
Utility
Semiconductor device and method of manufacturing the same
26 Oct 20
A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB.
Yoshinori Deguchi, Akinobu Watanabe
Filed: 24 Jun 20
Utility
Semiconductor device and method of manufacturing the same
26 Oct 20
In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation.
Digh Hisamoto, Yoshiyuki Kawashima
Filed: 1 Jul 19
Utility
Method of manufacturing semiconductor device
26 Oct 20
To provide, in an increased production yield, a reliability-improved semiconductor product having both a planar type transistor and a fin type transistor.
Shigeki Katou
Filed: 27 Mar 19
Utility
Semiconductor device and manufacturing method therefor
26 Oct 20
A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance.
Hitoshi Matsuura
Filed: 23 Jan 19
Utility
Semiconductor device with inductive coupling and method of manufacturing the same
26 Oct 20
A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.
Shinichi Uchida, Yasutaka Nakashiba, Tetsuya Iida, Shinichi Kuwabara
Filed: 15 Apr 18
Utility
Semiconductor integrated circuit device
26 Oct 20
In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film.
Hiromi Shigihara, Hiroshi Tsukamoto, Akira Yajima
Filed: 12 Sep 16
Utility
Semiconductor device and manufacturing method thereof
26 Oct 20
In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR.
Tomoo Nakayama, Shinichi Watanuki, Futoshi Komatsu, Teruhiro Kuwajima, Takashi Ogura, Hiroyuki Okuaki, Shigeaki Shimizu
Filed: 12 Nov 18
Utility
Method of manufacturing semiconductor device and semiconductor device
26 Oct 20
An improvement is achieved in the performance of a semiconductor device.
Toshiyuki Hata, Yuichi Yato
Filed: 21 Jul 17
Utility
Semiconductor module and method of manufacturing the same, and method of communication using the same
26 Oct 20
The semiconductor module includes a semiconductor chip and a semiconductor chip.
Tetsuya Iida, Yasutaka Nakashiba
Filed: 9 Oct 19
Utility
Semiconductor device and method of manufacturing the same
26 Oct 20
A semiconductor device capable of lowering a temperature coefficient and increasing a sheet resistance value (ρs value) and a manufacturing method thereof are provided.
Eisuke Kodama
Filed: 8 May 19
Utility
Semiconductor device having a ferroelectric memory and manufacturing method thereof
26 Oct 20
In a ferroelectric memory having a ferroelectric film between a gate electrode and a semiconductor substrate, dielectric breakdown of a gate insulating film is prevented and the polarization performance of the ferroelectric film is enhanced to improve the performance of a semiconductor device.
Tadashi Yamaguchi
Filed: 15 Nov 18
Utility
Motor driving system and motor driving method
26 Oct 20
Provided are a motor angle detector for detecting a motor angle, a current detector for detecting a motor current value to drive a motor, a vehicle inclination angle detector for detecting a vehicle inclination angle, a motor control circuit for outputting a control signal to control the driving of the motor, and a storage apparatus.
Yusuke Yasuda, Narihira Takemura
Filed: 25 Jul 18
Utility
Semiconductor Device and a Method of Manufacturing the Same
21 Oct 20
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate.
Shinya Suzuki
Filed: 2 Jul 20
Utility
Electronic device and method of manufacturing the same
19 Oct 20
A performance of an electronic device is improved.
Kazuaki Tsuchiyama, Motoo Suwa, Ryuichi Oikawa
Filed: 12 May 19
Utility
Cache memory device with access controller that accesses one of data memory and main memory based on retained cache hit determination result in response to next access
19 Oct 20
A cache memory device includes: data memory that stores cache data corresponding to data in main memory; tag memory that stores tag information to identify the cache data; an address estimation unit that estimates a look-ahead address to be accessed next; a cache hit determination unit that performs cache hit determination on the look-ahead address, based on the stored tag information; and an access controller that accesses the data memory or the main memory based on the retained cache hit determination result in response to a next access.
Tatsuhiro Tachibana
Filed: 15 Nov 17
Utility
Electronic device
19 Oct 20
An electronic device includes a wiring board and a semiconductor device on the wiring board's main surface.
Tatsuaki Tsukuda
Filed: 7 Apr 19
Utility
Semiconductor device and method of manufacturing the same
19 Oct 20
Assembly of the semiconductor device includes the following steps: (a) mounting a semiconductor chip on the bottom electrode 40; (b) mounting the top electrode 30 on the semiconductor chip; (c) forming a sealing body 70 made of resin and provided with a convex portion 74 so as to cover the semiconductor chip; and (d) exposing the electrode surface 31 of the top electrode 30 on the top surface of the sealing body 70 and exposing the electrode surface 41 of the bottom electrode 40 on the back surface of the sealing body 70.
Kuniharu Muto, Hideyuki Nishikawa
Filed: 12 May 19
Utility
Manufacturing method of semiconductor device and semiconductor device
19 Oct 20
A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.
Shoji Hashizume, Keita Takada
Filed: 25 Jun 19