1577 patents
Page 52 of 79
Utility
Semiconductor device, memory test method for semiconductor device, and test pattern generation program
14 Sep 20
To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address.
Tomonori Sasaki, Tatsuya Saito, Hideshi Maeno, Takeshi Ueki
Filed: 7 Apr 19
Utility
Semiconductor chip, semiconductor device, and electronic device
14 Sep 20
In order to improve reliability of a semiconductor device, in a semiconductor chip according to one embodiment, an uneven shape is formed on an exposed surface of a back surface electrode formed on a back surface of the semiconductor chip.
Kazuhiro Fukuchi
Filed: 3 Dec 15
Utility
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14 Sep 20
A performance of a semiconductor device is improved.
Yukihiro Sato, Toshinori Kiyohara
Filed: 14 Nov 19
Utility
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14 Sep 20
A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad.
Yoshinori Deguchi, Akinobu Watanabe
Filed: 22 Feb 16
Utility
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14 Sep 20
The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR.
Yuto Omizu, Takashi Hashimoto, Hideaki Yamakoshi
Filed: 5 May 19
Utility
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14 Sep 20
In a split-gate MONOS memory including a FINFET, occurrence of erroneous write in an unselected cell due to electric field concentration at an upper end of a fin is prevented, and thus reliability of a semiconductor device is improved.
Tomohiro Hayashi
Filed: 13 Nov 18
Utility
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9 Sep 20
An abnormality detection apparatus including a feature extraction circuit configured to extract a feature point and a feature value of a first image, and a feature point and a feature value of a second image, a flow calculation circuit configured to calculate, based on the feature value of the first image, a first abnormality detection circuit configured to detect an abnormality in the first image based on a first optical flow, and to detect an abnormality in the second image based on a third optical flow, and a second abnormality detection circuit configured to detect an abnormality in the first or second image based on a result of a comparison between the second optical flow and a fourth optical flow.
Yuki KAJIWARA, Kosuke Miyagawa, Masaki Nishibu, Kentaro Sasahara
Filed: 25 May 20
Utility
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9 Sep 20
A semiconductor device includes a substrate, an optical element, and a semiconductor element.
Seigo NAMIOKA, Yasutaka NAKASHIBA
Filed: 5 Mar 20
Utility
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9 Sep 20
A wireless communication system includes a wireless base station, a plurality of wireless terminals that communicate with the wireless base station using a first communication function, communicate with each other using a second communication function that consumes less power than the first communication function, and are driven by a battery, and a wireless controller.
Kazuhisa OKADA, Hiroki SUGIMOTO
Filed: 1 Mar 20
Utility
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7 Sep 20
Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed.
Shine C. Chung, Koji Nii
Filed: 13 Nov 18
Utility
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7 Sep 20
To provide a semiconductor device which suppresses a message image projected by a mobile from varying from a desired position.
Koji Yasuda, Hirofumi Kawaguchi, Akihide Takahashi
Filed: 6 Jun 19
Utility
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7 Sep 20
A semiconductor device according to one embodiment of the present invention includes a wire electrically connecting a die pad and a semiconductor chip mounted on the die pad to each other, and an encapsulation body encapsulating the semiconductor chip.
Jun Shibata
Filed: 13 Jan 19
Utility
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2 Sep 20
In a semiconductor device having MONOS memories configured by fin-type MISFETs, an increase in parasitic capacitance between wirings accompanying miniaturization of the semiconductor device is prevented, and the reliability of the semiconductor device is improved.
Tadashi YAMAGUCHI
Filed: 27 Feb 20
Utility
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2 Sep 20
Apparatus for performing offset cancellation is disclosed.
Mohsen Naghed
Filed: 30 Jul 17
Utility
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31 Aug 20
Performance of a semiconductor device is improved.
Shuuichi Kariyazaki, Kazuyuki Nakagawa, Keita Tsuchiya, Yosuke Katsura, Shinji Katayama, Norio Chujo, Masayoshi Yagyu, Yutaka Uematsu
Filed: 6 May 19
Utility
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31 Aug 20
A semiconductor device which simplifies the manufacturing process while decreasing the width of separation between a first MOS transistor area and a second MOS transistor area, and a method for manufacturing the semiconductor device.
Hiroshi Yanagigawa
Filed: 3 Sep 18
Utility
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31 Aug 20
A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.
Shinichi Shibahara, Daisuke Kawakami, Yutaka Igaku
Filed: 4 Nov 18
Utility
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31 Aug 20
There is a need to acquire more reliable profile information without relying on only the personal subjective judgment on the profile information.
Wataru Kurihara, Takehiro Mikami
Filed: 20 Feb 19
Utility
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26 Aug 20
The n-type body extension region BER is separated from the n+ buried region BL by the p-type impurity region PIR and is in contact with the p-type drift region DFT1.
Yuji ISHII
Filed: 5 Feb 20
Utility
xdork0ehh6saqxt4i5nzi8r6sd0o9nysd723q114gk7gzx8ef2
26 Aug 20
A control circuit connected to a control device configured to control a motor connected to a rotation shaft that is convertible into a turning angle of a turning wheel, the control circuit includes a main circuit configured to calculates a rotation number indicating a rotational state of the rotation shaft based on a detection signal from a rotation angle sensor configured to detect a rotation angle of the motor as a relative angle, a detection result communication unit configured to detect whether or not there is an abnormality in the main circuit and output a detection result to the control device, and a pseudo abnormality generating unit configured to set the detection result to be abnormal based on a pseudo abnormal signal from the control device.
Masato ODA, Kenichi KOZUKA, Hiromasa SUZUKI, Masashi OKI
Filed: 19 Feb 20