1577 patents
Page 56 of 79
Utility
Semiconductor integrated circuit device and semiconductor device
13 Jul 20
Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed.
Hiroyuki Takahashi, Muneaki Matsushige
Filed: 18 Feb 20
Utility
Method for manufacturing a semiconductor device having a step of performing ion implantation using a resist pattern as a mask
13 Jul 20
The reliability of a semiconductor device is improved.
Tomoo Nakayama, Tatsuya Usami
Filed: 22 Mar 18
Utility
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13 Jul 20
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained.
Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
Filed: 19 Mar 19
Utility
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8 Jul 20
In the conventional semiconductor device, it is impossible for two CPUs to operate memories to be debugged at synchronous timings.
Shinichi SUZAKI, Toshihiro KAWANO
Filed: 30 Dec 19
Utility
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6 Jul 20
An object of the present invention is to provide a highly-reliable content addressable memory.
Makoto Yabuuchi, Shinji Tanaka
Filed: 7 Mar 18
Utility
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6 Jul 20
According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor.
Yasuhiro Sugita, Koji Adachi, Yoichi Yuyama
Filed: 9 Nov 17
Utility
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6 Jul 20
A semiconductor device includes: memory cells, first word lined arranged for first ports and each arranging corresponding to respective rows of the memory cells; second word lines arranged for second ports and each arranged corresponding to respective rows of the memory cells, first dummy word lines each provided above the respective first word lines, second dummy word lines each provided above the respective second word lines, a word line driver driving the first and second word lines, and a dummy word line driver driving, in an opposite phase, the second dummy word line for the adjacent second word line according to driving of the first word line from among the first and second word lines, or the first dummy word line for the adjacent first word line according to driving of the second word line from among the first and second word lines.
Yuichiro Ishii
Filed: 14 Nov 18
Utility
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6 Jul 20
Provided is a semiconductor memory device having a low power consumption write assist circuit.
Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
Filed: 30 Oct 18
Utility
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6 Jul 20
Characteristics of a semiconductor device having a nonvolatile memory are improved.
Shunichi Narumi
Filed: 20 Nov 17
Utility
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6 Jul 20
An object of the present invention is to provide a power supply voltage stabilizing method that can suppress the performance of switching power supply from being deteriorated even when a battery voltage varies and/or load conditions change.
Masayuki Ida
Filed: 4 Sep 19
Utility
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6 Jul 20
A modulator includes an analog integrator including an analog circuit and a quantizer quantizing its output signal.
Takashi Oshima, Tetsuo Matsui, Mitsuya Fukazawa, Tomohiko Yano
Filed: 19 Feb 18
Utility
hqah53dpun5gpol6ro2swbgxzufpwyampqj0u2iil9edqqnxhvo
6 Jul 20
To shorten a processing time at boot time without lowering a security level, an acquiring unit acquires a public key, a signature generated with a secret key corresponding to the public key, and a program associated with the signature.
Seishiro Nagano, Shigenori Miyauchi
Filed: 26 Feb 18
Utility
2fsczz2ogqmtmxrkne81p8hfpabbrvy2ssqeylf6e7ojmo4k43m9te
1 Jul 20
A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI.
Makoto KOSHIMIZU, Hideki NIWAYAMA, Kazuyuki UMEZU, Hiroki SOEDA, Atsushi TACHIGAMI, Takeshi IIJIMA
Filed: 10 Mar 20
Utility
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1 Jul 20
An ultrasonic flow measurement system may include a signal generator configured to generate a first excitation signal for a first ultrasonic transducer and a second excitation signal for a second, different ultrasonic transducer.
Axel Kleinitz, Richard Dalby
Filed: 11 Jun 17
Utility
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1 Jul 20
A semiconductor device includes a first temperature sensor module, a second temperature sensor module, a first temperature controller, and a second temperature controller.
Tadashi KAMEYAMA, Masanori IKEDA
Filed: 17 Nov 19
Utility
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1 Jul 20
A semiconductor device includes an analog-digital conversion circuit that converts a voltage at a node between a reference resistor and a sensor resistor into output data, the reference resistor and the sensor resistor being connected in series.
Masuo OKUDA, Akemi WATANABE
Filed: 17 Dec 19
Utility
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1 Jul 20
The CPU includes a plurality of CPU cores.
Takahiko GOMI, Gaku INAMI, Ryu NAGASAWA
Filed: 17 Nov 19
Utility
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1 Jul 20
A semiconductor device capable of improving the efficiencies of communication systems is provided.
Keiichiro SANO, Jean Noel MOUTHE
Filed: 16 Dec 19
Utility
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1 Jul 20
A processing system includes a receiving circuit 1 for receiving an input signal from an externally connected sensor, an expected signal generating circuit 4 for automatically generating a teaching signal for use in the learning circuit 5, a learning circuit 5 for calculating a weight value, a bias value, and the like of the neural network model to form an expected signal from the teaching signal generated by the expected signal generating circuit 4 and the signal from the receiving circuit 1, an inference circuit 2 for performing signal processing based on a learned model of the neural network model generated by the learning circuit 5, and a validity verification circuit 3′ for performing similarity calculation between an output signal of the inference circuit 2 and an expected signal for comparison.
Yasushi WAKAYAMA
Filed: 9 Dec 19
Utility
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1 Jul 20
The semiconductor device includes a semiconductor chip including a first nonvolatile memory including a first memory block and a second memory block, CPU controlling the first nonvolatile memory, a first switch electrically connected to the first memory block and controlling the supply of the first power supply voltage to the first memory block, a second switch electrically connected to the second memory block and controlling the supply of the first power supply voltage to the second memory block, and a second nonvolatile memory electrically connected to each of the first switch and the second switch and storing flag information for controlling the first switch and the second switch, wherein the control of each of the first switch and the second switch is performed based on flag information indicating whether program data executed by CPU is written in the first memory block and the second memory block.
Kotaro SAKUMURA, Hiroshi TACHIBANA, Hideki OTSU
Filed: 2 Dec 19