1577 patents
Page 75 of 79
Utility
Memory Protection Circuit and Memory Protection Method
27 Nov 19
To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.
Takashi ICHIKAWA
Filed: 6 May 19
Utility
Semiconductor Device
27 Nov 19
Performance of a semiconductor device is improved.
Shuuichi KARIYAZAKI, Kazuyuki NAKAGAWA, Keita TSUCHIYA, Yosuke KATSURA, Shinji KATAYAMA, Norio CHUJO, Masayoshi YAGYU, Yutaka UEMATSU
Filed: 6 May 19
Utility
7lcbl6z5u2ma0t2t542z6kgm72o4bev9lda
27 Nov 19
The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR.
Yuto OMIZU, Takashi HASHIMOTO, Hideaki YAMAKOSHI
Filed: 5 May 19
Utility
lmlu7ysjzor5c6u2184wbm9zj71zgaixj3wnfs34vgj2ksysfxiuj
27 Nov 19
The terminal pattern TP1 of the wiring substrate PB has a side T1a facing the terminal pattern TP2 and the terminal pattern TP2 of the wiring substrate PB has a side T2a facing the side T1a of the terminal pattern TP1.
Takashi KARASHIMA
Filed: 5 May 19
Utility
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25 Nov 19
A semiconductor integrated circuit is described.
Masayasu Komyo, Yoichi Iizuka
Filed: 24 Oct 18
Utility
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25 Nov 19
A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell.
Yoshisato Yokoyama, Takeshi Hashizume, Toshiaki Sano
Filed: 6 Mar 18
Utility
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25 Nov 19
The semiconductor device includes a supply circuit for supplying a boosted voltage to a distal end of a wiring driven by a drive signal.
Shinji Tanaka, Makoto Yabuuchi
Filed: 13 Nov 17
Utility
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25 Nov 19
In manufacturing a trench type MOSFET, reliability of a semiconductor device is prevented from being degraded due to a short circuit or lowering of withstand voltage between a trench gate electrode and a source region.
Kazuya Horie, Katsuhiro Uchimura, Kazuhiro Toi, Masakazu Nakano
Filed: 5 Jul 17
Utility
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25 Nov 19
When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs.
Takao Kamoshima, Kojiro Horita, Shuji Matsuo
Filed: 22 Aug 17
Utility
9ebho27p8c91905600zqfkv1sacfc65w0motyqil
25 Nov 19
An electronic device has a first bus bar (conductor plate) connected to a first semiconductor device (semiconductor part) having a first power transistor; and a second bus bar (conductor plate) connected to a second semiconductor device (semiconductor part) having a second power transistor.
Tomohiro Nishiyama
Filed: 2 May 18
Utility
3oz2ojw406b0c32drvp8ha36d949sc3ei4ycahx37y0f9
25 Nov 19
In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member.
Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
Filed: 24 Sep 18
Utility
qohsoqexckswk256bnkya1hxqxfsq2zdz4xhxjl7c1pbdgbxcqxcp5ti
25 Nov 19
This invention is to improve a performance of a semiconductor device.
Yoshiyuki Kawashima, Takashi Hashimoto
Filed: 23 Feb 18
Utility
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25 Nov 19
A semiconductor device and a manufacturing method thereof according to the present invention include: a first pad electrode formed in an uppermost wiring layer of a multilayer wiring layer; a first insulating film formed on the first pad electrode; and a first organic insulating film formed over the first insulating film.
Tatsuya Usami
Filed: 22 May 18
Utility
6siixtxzhgld84g3go1zyx67ejjjw9n3en01dydal 9pbf81g0
25 Nov 19
An area of a semiconductor device having a FINFET can be reduced.
Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
Filed: 5 Aug 18
Utility
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25 Nov 19
Dan Aoki
Filed: 21 Mar 17
Utility
3pfacb4ps0ndmzqbzh8tig54dunei8g7qsz7yasckm18d654ev9
25 Nov 19
A reception unit (13) sequentially selects a plurality of sensor coils and receives a signal from a position indicator via the sensor coil that has been selected, and an operational circuit (14) detects, using an amplitude value and a phase value of the signal received by the reception unit (13) via each of the plurality of sensor coils, coordinates of a position indicated by the position indicator and a writing force of the position indicator.
Masato Hirai, Kosuke Fuwa
Filed: 15 Apr 17
Utility
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25 Nov 19
The size of a multi-processor is prevented from increasing even when the number of processor cores is increased.
Motoyasu Takabatake, Hisashi Shiota, Atsushi Nakamura, Yuji Chiba
Filed: 23 Oct 17
Utility
82dzl6wu6828obx6k67cpk90pnih3zf7b4j
20 Nov 19
A data processing device that can monitor properly the state of the interrupt processing of a virtual machine is provided.
Yasuhiro SUGITA
Filed: 5 May 19
Utility
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20 Nov 19
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede.
Takeshi KAWAMURA
Filed: 29 Jul 19
Utility
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20 Nov 19
A program is executed in an information processing device including a processor and a memory.
Tetsuji TSUDA, Teruki FUKUYAMA, Toshio SUNAMI
Filed: 30 Apr 19