1577 patents
Page 72 of 79
Utility
Semiconductor Device and Manufacturing Method of the Same
25 Dec 19
The semiconductor device includes an optical waveguide WG1 formed in a planar manner, and a three-dimensional optical waveguide WG2 optically connected with the optical waveguide WG1 and including a curved shape.
Tetsuya IIDA, Yasutaka NAKASHIBA
Filed: 10 Jun 19
Utility
Semiconductor Module, Manufacturing Method Thereof, and Communication Method Using the Same
25 Dec 19
The semiconductor device has an optical waveguide formed on a substrate, a first conductor film formed in the same layer as the optical waveguide, an insulating film formed on the first conductor film, a second conductor film formed on the insulating film, and a first interlayer insulating film formed on the substrate so as to cover the optical waveguide and the second conductor film.
Shinichi WATANUKI, Yasutaka NAKASHIBA
Filed: 13 May 19
Utility
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25 Dec 19
The access control circuit writes to the first storage unit a context information transmitted in one cycle from the CPU through the first bus, a context number identifying the context information, and a link context number identifying the context information transmitted from the CPU prior to the interrupt when the request for evacuating the task context information is received by the interrupt.
Tatsuhiro TACHIBANA
Filed: 5 Jun 19
Utility
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25 Dec 19
The semiconductor integrated circuit includes a plurality of CPUs (big CPU and LITTLE CPU).
Keita KOBAYASHI, Takahiko GOMI, Ryu NAGASAWA
Filed: 13 May 19
Utility
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25 Dec 19
Even under various conditions, stay of request on a bus is eliminated, and memory efficiency can be improved.
Yuki HAYAKAWA, Toshiyuki HIRAKI, Sho YAMANAKA
Filed: 10 Jun 19
Utility
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25 Dec 19
A master issues an access request to the memory.
Yuki HAYAKAWA, Toshiyuki HIRAKI, Sho YAMANAKA
Filed: 10 Jun 19
Utility
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23 Dec 19
A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.
Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
Filed: 20 Dec 18
Utility
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23 Dec 19
A performance of a semiconductor device is improved.
Yukihiro Sato, Toshinori Kiyohara
Filed: 22 Mar 18
Utility
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23 Dec 19
A semiconductor device which provides improved reliability.
Yoshiaki Sato, Shuuichi Kariyazaki, Kazuyuki Nakagawa
Filed: 18 Nov 17
Utility
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23 Dec 19
A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate.
Yoshihiko Shimanuki
Filed: 27 May 18
Utility
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23 Dec 19
Susumu Hirata
Filed: 30 Jan 18
Utility
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18 Dec 19
A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode.
Tsutomu OKAZAKI, Akira KATO, Kan YASUI, Kyoya NITTA, Digh HISAMOTO, Yasushi ISHII, Daisuke OKADA, Toshihiro TANAKA, Toshikazu MATSUI
Filed: 26 Aug 19
Utility
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18 Dec 19
A wireless transmission device includes an input terminal, control terminals, an amplifying circuit, a matching circuit, and an output terminal coupled to the output of the matching circuit.
Tomoumi YAGASAKI
Filed: 13 May 19
Utility
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18 Dec 19
The analog-to-digital converter includes a quantizer for outputting a quantized signal, a sampling circuit for sampling an analog input signal, a dithering circuit for generating an added voltage, and an integrating circuit for integrating a signal on which the added voltage is superimposed and outputting an integration result to the quantizer.
Akemi WATANABE
Filed: 13 May 19
Utility
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18 Dec 19
An A/D converter includes an A/D conversion circuit for converting an analog output signal into a digital signal, and a control circuit for controlling the A/D conversion circuit.
Yasuyuki TANAKA, Masaaki TANIMURA
Filed: 13 May 19
Utility
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18 Dec 19
A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.
Taro FUJII, Takao TOI, Teruhito TANAKA, Katsumi TOGAWA
Filed: 12 May 19
Utility
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18 Dec 19
The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.
Yasuhiro SUGITA
Filed: 13 May 19
Utility
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16 Dec 19
A semiconductor storage device provided can increase a write margin and suppress increase of a chip area.
Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
Filed: 18 Apr 18
Utility
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16 Dec 19
In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region.
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Kengo Masuda
Filed: 3 Jan 19
Utility
7b3er4zefkaq2yn0fg3yhqdpy46ew96xohsxzrmsax7ko
16 Dec 19
On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region.
Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
Filed: 4 Sep 17