28912 patents
Page 51 of 1446
Utility
Memory Device Structure with Data Storage Element
30 Nov 23
A semiconductor device structure is provided.
Hai-Dang TRINH, Hsing-Lien LIN, Cheng-Yuan TSAI
Filed: 25 Jul 23
Utility
Semiconductor Device and Method of Manufacture
30 Nov 23
Semiconductor devices and methods of manufacture are provided wherein a ferroelectric random access memory array is formed with bit line drivers and source line drivers formed below the ferroelectric random access memory array.
Meng-Han Lin, Sai-Hooi Yeong, Chi On Chui
Filed: 10 Aug 23
Utility
r1rnxk8maz7e5j8gys7phh6747rhasqpvawj4lfm2m1iqfiz0cwshts
30 Nov 23
A method of forming a memory device includes the following operations.
Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Tzu-Chiang Chen
Filed: 2 Aug 23
Utility
oyp761m64nevsydr9o5ocw640psr1ts1jjak9jvuzho3vf6lv0w1k7zbef
30 Nov 23
A semiconductor device is disclosed.
Tzu-Yu Chen, Sheng-Hung Shih, Fu-Chen Chang, Kuo-Chi Tu
Filed: 26 May 22
Utility
4y6yf7ciuomm8wcf7ixvl8gt7l0bo5k4u78m370e6hb8ef7lzuzjg0o
30 Nov 23
Disclosed herein are related to a device for performing neuromorphic computing.
Chieh Lee, Chia-En Huang, Yi-Chang Liu, Wen-Chang Cheng, Yih Wang
Filed: 25 May 22
Utility
n8pw8xcf82md4mw5eb6o72af4f7rp3ffj8nfs9e cd
30 Nov 23
In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate.
Kuan-Liang Liu, Sheng-Chau Chen, Chung-Liang Cheng, Chia-Shiung Tsai, Yeong-Jyh Lin, Pinyen Lin, Huang-Lin Chao
Filed: 9 Aug 23
Utility
vt4hvu3w5ul5js5cnveifzft13crz2f7bme x5528yt0
30 Nov 23
Disclosed herein are related to a memory device including a set of memory cells and a memory controller.
Perng-Fei Yuh, Yih Wang
Filed: 10 Aug 23
Utility
mls1u9hxucpb4c9n6jn2gmk91x0y8nd291tpkp13n7ek
30 Nov 23
In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.
Chenchen Jacob Wang, Sai-Hooi Yeong, Yu-Ming Lin, Chi On Chui
Filed: 9 Aug 23
Utility
i4dojvlraqjmg1qomti5ui5r9s3hbgdm6u2l3d8vwe0oo
30 Nov 23
A memory device and a method of operating the same are disclosed.
Chien-Yuan Chen, Hau-Tai Shieh, Cheng Hung Lee, Hung-Jen Liao
Filed: 8 Aug 23
Utility
5zdto2vpj10ahr19yceuh5ufqajb8dzs4oftrmaysd e094t
30 Nov 23
In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light.
Hong-Shyang Wu, Kuo-Ming Wu
Filed: 9 Aug 23
Utility
j1nhk4mx8i99636k0 xhrnvkb
30 Nov 23
First fire operations for an ovonic threshold switch (OTS) selector is provided.
Elia Ambrosi, Cheng-Hsien Wu, Hengyuan Lee, Chien-Min Lee, Xinyu BAO
Filed: 27 May 22
Utility
u5vjjjruc8wjxoy m4awj0ggqxu650rwqd7bbtt1i8fsb3x85yrn
30 Nov 23
A method of manufacturing a semiconductor structure includes forming a first dielectric layer surrounding an optical component.
Yu-Hao CHEN, Hui Yu LEE, Jui-Feng KUAN
Filed: 10 Aug 23
Utility
70swmntmkvggm70dqxzdsbunv397384ym03jll
30 Nov 23
A memory device includes a plurality of word lines (WLs).
Chun-Ying Lee, Chia-En Huang, Chieh Lee
Filed: 24 May 22
Utility
a2p4t7co0svpsqn 1uvryyc4wrdh5vgto5creq4g9v5j
30 Nov 23
A method for etching a magnetic tunneling junction (MTJ) structure is described.
Yi Yang, Dongna Shen, Vignesh Sundar, Yu-Jen Wang
Filed: 9 Aug 23
Utility
dl7khbfe8utejpyftt1c77taur5qafjh gwsfgta4a8pbik
30 Nov 23
Disclosed herein are related to a memory array including one-time programmable (OTP) cells.
Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
Filed: 10 Aug 23
Utility
bi3s4itzqty6l8umrvhv9d3aim5pbhi565ufj06
30 Nov 23
An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack.
Yi Yang, Yu-Jen Wang
Filed: 28 Jul 23
Utility
1ox2g2wsfp0plcr6 etpj1eiip60
30 Nov 23
A pre-treatment apparatus can be added as a module of a wafer track system, where the pre-treatment is designed to reduce friction at the edges of a substrate.
Chun-Hsiang WANG, Kai Yuan CHAN, Po-Chung CHENG, Chien Chou KO
Filed: 23 Mar 23
Utility
0sa988uuu4aw723wpasd45bats9wg8s7zhb8wb939vxh
30 Nov 23
A semiconductor device includes a substrate with a metal line embedded in the substrate, a dielectric layer disposed on the substrate, a bottom electrode via extending through the dielectric layer and landing on a top surface of the metal line, a bottom electrode disposed on a top surface of the bottom electrode via, a magnetic tunneling junction stack disposed on a top surface of the bottom electrode, and a top electrode disposed on the magnetic tunneling junction stack.
Hsiang-Ku Shen, Liang-Wei Wang, Dian-Hau Chen
Filed: 29 Jul 23
Utility
e9nx7x1ykpcffmz305m78rovtkslaolaii8wlkpgoaacmdr5
30 Nov 23
A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer.
Pei-Yu Chou, Tze-Liang Lee
Filed: 7 Aug 23
Utility
2tpq7wa6nzmhb36givmbqo6j5r792svwrf9s2k5v2f127i
30 Nov 23
A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
Filed: 10 Aug 23