28912 patents
Page 47 of 1446
Utility
Bond wave optimization method and device
5 Dec 23
A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die.
Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
Filed: 14 Feb 22
Utility
Integrated circuit, interface circuit and method
5 Dec 23
An integrated circuit includes first and second arrays of resistors, and a plurality of interface circuits.
Mei-Chen Chuang
Filed: 31 Aug 21
Utility
Memory sense amplifier with precharge
5 Dec 23
A memory device includes a memory cell and a sense amplifier.
Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
Filed: 26 May 22
Utility
Systems and methods to detect cell-internal defects
5 Dec 23
A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.
Ankita Patidar, Sandeep Kumar Goel
Filed: 5 Apr 22
Utility
Magnetic memory device
5 Dec 23
The present disclosure describes a magnetic memory device.
Chia-Hsiang Chen, Chih-Yang Chang, Chia Yu Wang, Meng-Chun Shih
Filed: 21 Jun 22
Utility
Atom probe tomography specimen preparation
5 Dec 23
The disclosure is directed to techniques in preparing an atom probe tomography (“APT”) specimen.
Shih-Wei Hung, Jang Jung Lee
Filed: 19 Aug 20
Utility
Method and structure for diodes with backside contacts
5 Dec 23
A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.
Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
Filed: 31 Aug 21
Utility
Robot arm device and method for transferring wafer
5 Dec 23
A method includes positioning an end effector at a height lower than a height of a wafer.
Wei-Hua Houng, Che-Fu Chen
Filed: 12 Apr 21
Utility
Reticle transportation container
5 Dec 23
A transportation container is provided with a container body constructed of a top wall, a bottom wall, a rear wall, and two sidewalls forming a front opening for loading or unloading a reticle pod into or out of the container body; a lid for opening and closing the front opening; and a lift plate above the container body configured to connect to a carrier of an overhead hoist transfer (OHT) system.
Yu-Ching Lee, Yu-Piao Fang
Filed: 16 Apr 21
Utility
Selective deposition of metal barrier in damascene processes and the structures formed thereof
5 Dec 23
A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor.
Chia-Pang Kuo, Ya-Lien Lee, Chieh-Yi Shen
Filed: 30 Jun 22
Utility
Semiconductor package and methods of forming the same
5 Dec 23
A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.
Meng-Che Tu, Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
Filed: 7 Jun 21
Utility
Self-aligned structure for semiconductor devices
5 Dec 23
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures.
Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng, Kuan-Ting Pan
Filed: 8 Mar 21
Utility
Formation of hybrid isolation regions through recess and re-deposition
5 Dec 23
A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions.
Chung-Ting Ko, Chi On Chui
Filed: 20 Jul 22
Utility
FinFET devices and methods of forming the same
5 Dec 23
Provided are FinFET devices and methods of forming the same.
Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Ching, Chun-Hsiung Lin, Pei-Hsun Wang
Filed: 23 Nov 20
Utility
Gate structure and method of forming same
5 Dec 23
A semiconductor device and a method of forming the same are provided.
Shahaji B. More, Chandrashekhar Prakash Savant, Chun Hsiung Tsai
Filed: 11 Jul 22
Utility
Semiconductor device and method
5 Dec 23
A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material.
Yin-Jie Pan, Yu-Yun Peng
Filed: 26 Apr 21
Utility
Packaged semiconductor devices with wireless charging means
5 Dec 23
A semiconductor device package is provided.
Chen-Hua Yu, Hao-Yi Tsai, Tzu-Sung Huang, Ming-Hung Tseng, Hung-Yi Kuo
Filed: 10 Feb 22
Utility
Semiconductor package structure and method for manufacturing the same
5 Dec 23
A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound.
Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
Filed: 24 Jun 19
Utility
Semiconductor devices including decoupling capacitors
5 Dec 23
Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed.
Yu-Xuan Huang, Hou-Yu Chen, Ching-Wei Tsai, Kuan-Lun Cheng, Chung-Hui Chen
Filed: 15 Jul 22
Utility
Semiconductor memory structure and interconnect structure of semiconductor memory structure
5 Dec 23
A semiconductor memory structure includes a first cell, a second cell, a first bit line, a first source line, a second bit line and a second source line.
Meng-Han Lin, Sai-Hooi Yeong, Chenchen Wang
Filed: 5 Jan 21