28912 patents
Page 43 of 1446
Utility
3D Stacking Architecture Through TSV and Methods Forming Same
7 Dec 23
A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer.
Hsien-Wei Chen, Jie Chen, Shin-Puu Jeng
Filed: 2 Jun 22
Utility
Heterostructure Channel Layer for Semiconductor Devices
7 Dec 23
The present disclosure describes a semiconductor structure having a heterostructure channel layer.
W.Y. LIN, H.S. Hu, Chao-Chi Chen
Filed: 6 Jun 22
Utility
ib3px3z9673yl6zl9zplp64pnnba2rk9m1
7 Dec 23
A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer.
Li-Ling LIAO, Ming-Chih YEW, Chia-Kuei HSU, Shin-Puu JENG
Filed: 6 Jun 22
Utility
hmcst1wizybrtazxzmx45z 4vsowc
7 Dec 23
A method includes forming a fin over a substrate, the fin comprising alternately stacking first oxide-based semiconductor layers and second oxide-based semiconductor layers, removing the second oxide-based semiconductor layers to form a plurality of spaces each between corresponding ones of the first oxide-based semiconductor layers, and depositing in sequence a gate dielectric layer and a gate metal into the plurality of spaces each between corresponding ones of the second oxide-based semiconductor layers.
Jih-Chao CHIU, Song-Ling LI, Chee-Wee LIU
Filed: 1 Jun 22
Utility
eea7zaoeacditrw0oepxnzi2essci146q0zn13swi5f92oioxcstyukfh2
7 Dec 23
Some implementations described herein provide techniques and apparatuses for a semiconductor package.
Po-Chen LAI, Ming-Chih YEW, Shu-Shen YEH, Po-Yao LIN, Shin-Puu JENG
Filed: 2 Jun 22
Utility
j3l1dbok2r eotmmfg9hx6vt4jff135qo26n4kal83ms3w2mq
7 Dec 23
Disclosed are a chemical mechanical polishing apparatus, a control method for the chemical mechanical polishing apparatus and a chemical mechanical polishing system.
Te-Chien Hou, Wen-Pin Liao, Chen-Chi Tang, Shich-Chang Suen, Kei-Wei Chen
Filed: 6 Jun 22
Utility
fbqbunumv3hx65r3iyxrq42pxo62gxws5obd7iru91i8uly
7 Dec 23
A semiconductor structure includes a substrate having a seal ring region and a circuit region, a dielectric interlayer over the substrate, one or more dielectric layers disposed over the dielectric interlayer, a connection structure disposed in the one or more dielectric layers in the seal ring region, and a metal plug disposed below the connection structure and disposed at least partially in the dielectric interlayer in the seal ring region.
Hsien-Wei Chen
Filed: 8 Aug 23
Utility
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7 Dec 23
The disclosure provides a voltage droop monitor (VDM) and a voltage droop monitoring method.
Chin-Ming Fu
Filed: 17 Jun 23
Utility
ry3mym a1ncgmwugtq8pa5iriu5dlu4v02iqqiu
7 Dec 23
Semiconductor structures and methods are provided.
Kuei-Ming Chen, Chi-Ming Chen, Shih-Pang Chang
Filed: 3 Jun 22
Utility
81q9nfstcd8pu15vjr4bj3z2anuwv3ynfq5iqi37y421njozg7dp
7 Dec 23
An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal.
Martin Kinyua
Filed: 21 Aug 23
Utility
6pm85ax1p9vvaclk3sknb6ce
7 Dec 23
The present disclosure provides a semiconductor structure that includes a substrate having a circuit region and a seal ring region around the circuit region; first active regions of a first width W1 formed in the circuit region; second active regions of a second width W2 formed in the seal ring region; first gate stacks disposed on the first active regions in the circuit region and extending to isolation features; and second gate stacks disposed on the second active regions in the seal ring region and completely landing on the second active regions.
Chun Yu CHEN, Yen Lian LAI
Filed: 6 Jun 22
Utility
atsgsssmoqhcuu9srf54r7ufrv5el2e4k6ujo7iv9ll 20t6
7 Dec 23
A 3D memory array including multiple memory cells and a method of manufacturing the same are provided.
Yu-Wei Jiang, TsuChing Yang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
Filed: 5 Jun 22
Utility
7akmypzthykjpyqh72k084zpfs8q6u5lh 2lfb911r22l
7 Dec 23
A method of forming a semiconductor structure includes forming a photoresist over a first conductive pattern.
Feng-Wei KUO, Wen-Shiang LIAO
Filed: 24 Jul 23
Utility
6gnt9hi5k5gbdtlbayx3d2tl7l5
7 Dec 23
Provided is a memory cell including a selector disposed over a substrate, a memory element and a connecting pad.
Yu-Chao Lin, Tung-Ying Lee
Filed: 2 Jun 22
Utility
clqopepdir513x7jx7veaob9ladf0pkub5ypbok4ihv3z4i
7 Dec 23
In some embodiments, the present disclosure relates to a device that includes an interconnect structure arranged on a frontside of a substrate.
Ming Chyi Liu
Filed: 8 Aug 23
Utility
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7 Dec 23
A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.
Ya-Jui TSOU, Jih-Chao CHIU, Huan-Chi SHIH, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
Filed: 2 Jun 22
Utility
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7 Dec 23
A multi-die package includes a plurality of non-active dies among the IC dies included in the multi-die package.
Chia-Kuei HSU, Ming-Chih YEW, Tsung-Yen LEE, Shin-Puu JENG
Filed: 18 Jul 22
Utility
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7 Dec 23
A semiconductor device includes a substrate, an interconnect, and a sensor.
Wei Lee, Chung-Liang Cheng, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
Filed: 2 Jun 22
Utility
jzrmwzvqofnwmwkgh0v29jfmoqb06pjhg9kskwidnxb0vdfp7m95
7 Dec 23
A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component.
Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou
Filed: 8 Aug 23
Utility
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7 Dec 23
A semiconductor device includes a substrate, an interconnect, a second transistor, and a sensing film.
Wei Lee, Chung-Liang Cheng, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
Filed: 2 Jun 22