28912 patents
Page 43 of 1446
Utility
Packages with Multiple Types of Underfill and Method Forming the Same
7 Dec 23
A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component.
Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou
Filed: 8 Aug 23
Utility
Package Structure and Method of Forming the Same
7 Dec 23
A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure.
Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
Filed: 2 Aug 23
Utility
Package and Method for Forming the Same
7 Dec 23
A package is provided in accordance with some embodiments.
Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
Filed: 1 Jun 22
Utility
Surface Uniformity Control In Pixel Structures of Image Sensors
7 Dec 23
A semiconductor device with an image sensor and a method of fabricating the same are disclosed.
Po-Chun LIU, Eugene I-Chun CHEN, Chun-Kai LAN
Filed: 8 Aug 23
Utility
Device Including Mim Capacitor and Resistor
7 Dec 23
A method of making a semiconductor device, includes: providing a first dielectric layer; sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.
Chen-Hsiang HUNG, Li-Hsin CHU, Chia-Ping LAI, Chung-Chuan TSENG
Filed: 10 Aug 23
Utility
Integrated Circuit, Transistor and Mehtod of Fabricating the Same
7 Dec 23
A transistor includes a gate electrode, a gate dielectric, a channel layer and a source line and bit line.
Yi-Cheng Chu, Tzu-Hsiang Hsu, Pin-Cheng Hsu, Chung-Te Lin
Filed: 6 Jun 22
Utility
Structure and Method for Gate-all-around Metal-oxide-semiconductor Devices with Improved Channel Configurations
7 Dec 23
The present disclosure provides an integrated circuit device that comprises a semiconductor substrate having a top surface; a first and a second source/drain features over the semiconductor substrate; a first semiconductor layer extending in parallel with the top surface and connecting the first and the second source/drain features, the first semiconductor layer having a center portion and two end portions, each of the two end portions connecting the center portion and one of the first and second source/drain features; a first spacer over the two end portions of the first semiconductor layer; a second spacer vertically between the two end portions of the first semiconductor layer and the top surface; and a gate electrode wrapping around and engaging the center portion of the first semiconductor layer.
Jhon Jhy Liaw
Filed: 10 Aug 23
Utility
System, Control Method and Apparatus for Chemical Mechanical Polishing
7 Dec 23
Disclosed are a chemical mechanical polishing apparatus, a control method for the chemical mechanical polishing apparatus and a chemical mechanical polishing system.
Te-Chien Hou, Wen-Pin Liao, Chen-Chi Tang, Shich-Chang Suen, Kei-Wei Chen
Filed: 6 Jun 22
Utility
Semiconductor Devices With Reduced Leakage Current And Methods Of Forming The Same
7 Dec 23
Semiconductor devices and methods are provided.
Yu-Hsuan Lin, Chun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jian-Hao Chen
Filed: 4 Jun 22
Utility
Analog to Digital Converter with Inverter Based Amplifier
7 Dec 23
An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal.
Martin Kinyua
Filed: 21 Aug 23
Utility
Multi-Gate Devices And Method Of Forming The Same
7 Dec 23
Semiconductor structures and methods of forming the same are provided.
Ming-Lung Cheng, Huang-Hsuan Lin, Chih Chieh Yeh
Filed: 3 Jun 22
Utility
Voltage Droop Monitor and Voltage Droop Monitoring Method
7 Dec 23
The disclosure provides a voltage droop monitor (VDM) and a voltage droop monitoring method.
Chin-Ming Fu
Filed: 17 Jun 23
Utility
Contacts for Highly Scaled Transistors
7 Dec 23
A semiconductor device and methods of forming the same are disclosed.
Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
Filed: 27 Jul 23
Utility
Memory Device and Formation Method Thereof
7 Dec 23
A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.
Ya-Jui TSOU, Jih-Chao CHIU, Huan-Chi SHIH, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
Filed: 2 Jun 22
Utility
Method for Fabricating Metal Gate Devices and Resulting Structures
7 Dec 23
A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
Filed: 25 Jul 23
Utility
Memory Cell, Memory Array and Manufacturing Method Thereof
7 Dec 23
A 3D memory array including multiple memory cells and a method of manufacturing the same are provided.
Yu-Wei Jiang, TsuChing Yang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
Filed: 5 Jun 22
Utility
Ldmos with Enhanced Safe Operating Area and Method of Manufacture
7 Dec 23
An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.
Lianjie LI, Feng HAN, Jian-Hua LU, YanBin LU, Shui Liang CHEN
Filed: 10 Aug 23
Utility
Semiconductor Device, Memory Cell and Method of Forming the Same
7 Dec 23
Provided is a memory cell including a selector disposed over a substrate, a memory element and a connecting pad.
Yu-Chao Lin, Tung-Ying Lee
Filed: 2 Jun 22
Utility
Method of Cleaning, Support, and Cleaning Apparatus
7 Dec 23
A method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support.
Yi Chen HO, Chih Ping LIAO, Ker-hsun LIAO, Chi-Hsun LIN
Filed: 6 Jun 22
Utility
Semiconductor Device and Manufacturing Method Thereof
7 Dec 23
A semiconductor device includes a substrate, an interconnect, and a sensor.
Wei Lee, Chung-Liang Cheng, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
Filed: 2 Jun 22