28912 patents
Page 40 of 1446
Utility
Semiconductor device having staggered gate-stub-size profile and method of manufacturing same
12 Dec 23
A method generating the layout diagram includes: selecting gate patterns for which a first distance from a corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each of the selected gate patterns, increasing a size of the corresponding cut-gate section from a first value to a second value; the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern; and the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern.
Te-Hsin Chiu, Shih-Wei Peng, Jiann-Tyng Tzeng
Filed: 1 Dec 20
Utility
CMOS image sensor having indented photodiode structure
12 Dec 23
The present disclosure relates to a CMOS image sensor, and an associated method of formation.
Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
Filed: 17 Nov 21
Utility
Isolation features and methods of fabricating the same
12 Dec 23
Semiconductor devices and methods of fabricating semiconductor devices are provided.
I-Wen Wu, Fu-Kai Yang, Chen-Ming B. Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
Filed: 17 May 21
Utility
Gate etch back with reduced loading effect
12 Dec 23
A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface.
Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin, Pinyen Lin
Filed: 1 Jul 22
Utility
Structures and methods for controlling dopant diffusion and activation
12 Dec 23
Structures and methods for controlling dopant diffusion and activation are disclosed.
Ching-Yu Chen, Wei-Ting Chang, Yu-Shine Lin, Jiang-He Xie
Filed: 18 Aug 21
Utility
Integration of p-channel and n-channel E-FET III-V devices without parasitic channels
12 Dec 23
In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate.
Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
Filed: 24 May 22
Utility
Memory cell and method of forming the memory cell
12 Dec 23
A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.
Meng-Sheng Chang, Chia-En Huang
Filed: 7 Apr 20
Utility
Flat bottom electrode via (BEVA) top surface for memory
12 Dec 23
Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method.
Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
Filed: 30 Nov 21
Utility
Magnetic tunneling junction with synthetic free layer for SOT-MRAM
12 Dec 23
A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure.
Chien-Min Lee, Shy-Jay Lin
Filed: 8 Jan 21
Utility
Semiconductor device including trimmed-gates and method of forming same
12 Dec 23
A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.
Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
Filed: 21 Feb 23
Utility
Non-volatile memory (NVM) cell structure to increase reliability
12 Dec 23
Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate.
Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
Filed: 30 Jun 22
Utility
Method to improve magnetic tunnel junction memory cells by treating native oxide
12 Dec 23
Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided.
Jung-Tang Wu, Meng Yu Wu, Szu-Hua Wu, Chin-Szu Lee
Filed: 26 Apr 21
Utility
Memory structure and method of forming the same
12 Dec 23
A method of forming a memory structure includes the following steps.
Shih-Hsuan Chien, Meng-Han Lin, Han-Wei Wu, Feng-Cheng Yang
Filed: 26 Apr 21
Utility
FeRAM with laminated ferroelectric film and method forming same
12 Dec 23
A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer.
Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
Filed: 9 Aug 22
Utility
Method and System for Adjusting Location of a Wafer and a Top Plate In a Thin-film Deposition Process
7 Dec 23
A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process.
Yu-Hsiang CHENG, Che-Wei WU
Filed: 7 Aug 23
Utility
Conductive Structures
7 Dec 23
Provided is a conductive structure and a method for forming such a structure.
Yi-Hsiang Chao, Shu-Lan Chang, Ching-Yi Chen, Shih-Wei Yeh, Pei Shan Chang, Ya-Yi Cheng, Yu-Chen Ko, Yu-Shiuan Wang, Chun-Hsien Huang, Hung-Chang Hsu, Chih-Wei Chang, Ming-Hsing Tsai, Wei-Jung Lin
Filed: 1 Jun 22
Utility
System and Method for Measuring Magnetic Fields In PVD System
7 Dec 23
A semiconductor processing system includes a first semiconductor processing site and a second semiconductor processing site.
Mei-Hsuan LIN, Rong Syuan FAN, Jen-Yuan CHANG
Filed: 3 Jun 22
Utility
Method of Forming Semiconductor Device
7 Dec 23
A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer.
Ting-Li Yang, Wen-Hsiung Lu, Jhao-Yi Wang, Fu Wei Liu, Chin-Yu Ku
Filed: 2 Aug 23
Utility
Semiconductor Device with Leakage Current Suppression and Method for Forming the Same
7 Dec 23
A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.
Bo-Yu Lai, Jyun-Chih Lin, Yen-Ting Chen, Wei-Yang Lee, Chia-Pin Lin, Wei Hao Lu, Li-Li Su
Filed: 10 Aug 23
Utility
Conductive Structure Interconnects
7 Dec 23
Provided are devices with conductive contacts and methods for forming such devices.
Tzu Pei Chen, Chia-Hao Chang, Shin-Yi Yang, Chia-Hung Chu, Po-Chin Chang, Shuen-Shin Liang, Chun-Hung Liao, Yuting Cheng, Hung-Yi Huang, Harry Chien, Pinyen Lin, Sung-Li Wang
Filed: 1 Jun 22