28912 patents
Page 42 of 1446
Utility
Wafer Transportation
7 Dec 23
System and method for cross-fab wafer transportation are provided.
Chieh Hsu, Guancyun Li, Ching-Jung Chang, Chi-Feng Tung
Filed: 4 Jun 22
Utility
Semiconductor Structure
7 Dec 23
A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure.
Shih-Hao LIN, Chia-Hung CHOU, Chih-Hsuan CHEN, Ping-En CHENG, Hsin-Wen SU, Chien-Chih LIN, Szu-Chi YANG
Filed: 10 Aug 23
Utility
Semiconductor Packages and Methods of Forming
7 Dec 23
A method of forming a semiconductor structure includes: forming a first redistribution structure on a first side of a wafer, the first redistribution structure including dielectric layers and conductive features in the dielectric layers; forming grooves in the first redistribution structure, the grooves exposing sidewalls of the dielectric layers and the wafer, the grooves defining a plurality of die attaching regions; bonding a plurality of dies to the first redistribution structure in the plurality of die attaching regions; forming a first molding material on the first side of the wafer around the plurality of dies, the first molding material filling the grooves; forming a passivation layer on a second side of the wafer opposing the first side; and dicing along the grooves from the second side of the wafer to form a plurality of individual semiconductor packages, each of the plurality of individual semiconductor packages including a respective die.
Cheng-Chieh Li, Chih-Wei Wu, Ying-Ching Shih
Filed: 2 Jun 22
Utility
Semiconductor Device with Oxide-based Semiconductor Channel
7 Dec 23
A method includes forming a fin over a substrate, the fin comprising alternately stacking first oxide-based semiconductor layers and second oxide-based semiconductor layers, removing the second oxide-based semiconductor layers to form a plurality of spaces each between corresponding ones of the first oxide-based semiconductor layers, and depositing in sequence a gate dielectric layer and a gate metal into the plurality of spaces each between corresponding ones of the second oxide-based semiconductor layers.
Jih-Chao CHIU, Song-Ling LI, Chee-Wee LIU
Filed: 1 Jun 22
Utility
Semiconductor Package and Methods of Manufacturing
7 Dec 23
A semiconductor package, which may correspond to a high-performance computing package, includes an interposer, a substrate, and an integrated circuit device between the interposer and the substrate.
Po-Chen LAI, Ming-Chih YEW, Li-Ling LIAO, Yu-Sheng LIN, Shin-Puu JENG
Filed: 6 Jun 22
Utility
Power Mode Wake-up for Memory on Different Power Domains
7 Dec 23
A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array.
Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
Filed: 4 Aug 23
Utility
High Bandwidth Package Structure
7 Dec 23
A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.
Harry-Haklay Chuang, Wen-Tuo Huang, Wei-Cheng Wu, Yu-Ling Hsu, Pai Chi Chou, Ya-Chi Hung
Filed: 2 Jun 22
Utility
Wafer Bonding Method and Semiconductor Structure Obtained by the Same
7 Dec 23
A method for manufacturing a semiconductor structure includes: forming a semiconductor device on a main region of the device substrate, the device substrate having a peripheral region surrounding the main region; forming a first filling layer on the peripheral region of the device substrate; forming a second filling layer over the first filling layer and the semiconductor device after forming the first filling layer, the second filling layer having a polishing rate different from that of the first filling layer; performing a planarization process over the second filling layer to remove a portion of the second filling layer so that a remaining portion of the second filling layer has a planarized surface opposite to the device substrate; and bonding the device substrate to a carrier substrate through the first filling layer and the remaining portion of the second filling layer.
Pei-Yu CHOU, Yen-Yu CHEN, Meng-Ku CHEN, Shiang-Bau WANG, Tze-Liang LEE
Filed: 6 Jun 22
Utility
Redistribution Layer Structure with Support Features and Methods
7 Dec 23
A device includes a semiconductor chip and a redistribution layer (RDL) structure connected to the semiconductor chip.
Monsen Liu, Shang-Lun Tsai, Shuo-Mao Chen, Shin-Puu Jeng
Filed: 3 Jun 22
Utility
Electrostatic Discharge (Esd) Array with Circuit Controlled Switches
7 Dec 23
An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein.
Tao-Yi HUNG, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen
Filed: 10 Aug 23
Utility
Method of Manufacturing Semiconductor Packages
7 Dec 23
A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer.
Li-Ling LIAO, Ming-Chih YEW, Chia-Kuei HSU, Shin-Puu JENG
Filed: 6 Jun 22
Utility
Transistor and Manufacturing Method of the Same
7 Dec 23
A transistor includes a first conductive type channel layer, a second conductive type channel layer, a gate structure, first source/drain regions and second source/drain regions.
Marcus Johannes Henricus Van Dal
Filed: 5 Jun 22
Utility
Advanced Seal Ring Structure and Method of Making the Same
7 Dec 23
A semiconductor structure includes a substrate having a seal ring region and a circuit region, a dielectric interlayer over the substrate, one or more dielectric layers disposed over the dielectric interlayer, a connection structure disposed in the one or more dielectric layers in the seal ring region, and a metal plug disposed below the connection structure and disposed at least partially in the dielectric interlayer in the seal ring region.
Hsien-Wei Chen
Filed: 8 Aug 23
Utility
Seam-top Seal for Dielectrics
7 Dec 23
A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface.
Kuei-Lin CHAN, Fu-Ting YEN, Yu-Yun PENG, Keng-Chu LIN
Filed: 6 Jun 22
Utility
Multi-Channel Device with Seal Ring Structure and Method Making the Same
7 Dec 23
The present disclosure provides a semiconductor structure that includes a substrate having a circuit region and a seal ring region around the circuit region; first active regions of a first width W1 formed in the circuit region; second active regions of a second width W2 formed in the seal ring region; first gate stacks disposed on the first active regions in the circuit region and extending to isolation features; and second gate stacks disposed on the second active regions in the seal ring region and completely landing on the second active regions.
Chun Yu CHEN, Yen Lian LAI
Filed: 6 Jun 22
Utility
Sense Amplifier and Method Thereof
7 Dec 23
A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals.
Tsung-Che LU, Chin-Ming FU, Chih-Hsien CHANG
Filed: 1 Jun 22
Utility
Manufacturing Method of Semiconductor Structure
7 Dec 23
A method of forming a semiconductor structure includes forming a photoresist over a first conductive pattern.
Feng-Wei KUO, Wen-Shiang LIAO
Filed: 24 Jul 23
Utility
Semiconductor Devices and Method of Forming the Same
7 Dec 23
A method of forming a semiconductor device includes the following steps.
Yu-Ting Hsiao, Min-Hsiu Hung, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
Filed: 6 Jun 22
Utility
Multiple Non-active Dies In a Multi-die Package
7 Dec 23
A multi-die package includes a plurality of non-active dies among the IC dies included in the multi-die package.
Chia-Kuei HSU, Ming-Chih YEW, Tsung-Yen LEE, Shin-Puu JENG
Filed: 18 Jul 22
Utility
Substrate Retaining Assembly and Door Device
7 Dec 23
A door device includes a door body and a substrate retaining assembly.
Ming-Chien CHIU, Chia-Ho CHUANG, Kuo-Hua LEE, Jyun-Ming LYU, Tzu Ang CHIANG, Yi-Feng HUANG, Tsung-Yi LIN
Filed: 23 May 23