28912 patents
Page 45 of 1446
Utility
Semiconductor Structure and Method for Forming the Same
7 Dec 23
A method for forming a semiconductor structure is provided.
Tai-Yuan WANG
Filed: 6 Jun 22
Utility
Semiconductor Device with Gate Isolation Features and Fabrication Method of the Same
7 Dec 23
A semiconductor device includes a first channel member over a first backside dielectric feature, a first gate structure engaging the first channel member, a second channel member over a second backside dielectric feature, a second gate structure engaging the second channel member, and a first isolation feature includes a first portion laterally between the first and second backside dielectric features and a second portion laterally between the first and second gate structures.
Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Jia-Chuan You, Chia-Hao Chang, Chih-Hao Wang, Kuan-Lun Cheng
Filed: 10 Aug 23
Utility
25fv6dc7m9vshwddj6e5v v16w23gr
7 Dec 23
A semiconductor device and methods of forming the same are disclosed.
Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
Filed: 27 Jul 23
Utility
nmotttuhusd2tlb2i2xy3gphf5nyzaal5jdhql6pohyyk5ku1thr73k2
7 Dec 23
A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
Filed: 25 Jul 23
Utility
2uzeuwi5yn2kaguz433tj6z v7z7indm
7 Dec 23
Semiconductor device and the manufacturing method thereof are disclosed.
Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Chih-Hao Wang
Filed: 9 Aug 23
Utility
k28y07e3kp71ir6r6tt2fkivjd0
7 Dec 23
A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate.
Yu-Ming CHEN, Szu-Ying CHEN, Yen-Chun HUANG, Sen-Hong SYUE, Huicheng CHANG, Yee-Chia YEO
Filed: 3 Jun 22
Utility
wfcjrofxg49pot5xzoh8yiey5
7 Dec 23
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
Filed: 2 Aug 23
Utility
pazrl9d3jt8j8ajydfmmt73k5sr765x20f5kf9e0e90zwio0
7 Dec 23
An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.
Lianjie LI, Feng HAN, Jian-Hua LU, YanBin LU, Shui Liang CHEN
Filed: 10 Aug 23
Utility
hr9nrldjn22lfwaw272rv6afv 184a8e2lewu0ns3
7 Dec 23
A semiconductor structure according to the present disclosure includes a first p-type epitaxial feature disposed over a first fin, a second p-type epitaxial feature disposed and spanning over a second fin and a third fin, an interlayer dielectric (ILD) layer over the first p-type epitaxial feature and the second p-type epitaxial feature, a first contact extending through the ILD layer to electrically couple to the first p-type epitaxial feature, and a second contact extending through the ILD layer to electrically coupled to the second p-type epitaxial feature.
Shahaji B. More
Filed: 2 Jun 22
Utility
7ot3wo hq5yjbynjh01dgoh87gad4smjlkaf0rjh2neyxy83rxw
7 Dec 23
A method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support.
Yi Chen HO, Chih Ping LIAO, Ker-hsun LIAO, Chi-Hsun LIN
Filed: 6 Jun 22
Utility
ygdo727yo2b8c7y5yzbq6uodzy979sznurdk65jzm ds
7 Dec 23
A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.
Chung-Cheng Chou, Tien-Yen Wang
Filed: 4 Aug 23
Utility
5uvd8q2ic ekb77nqbna24ph97qu5l88txlcg08tqbt7vm
7 Dec 23
A micromechanical arm array is provided.
Shih-Yu Liao, Tsai-Hao Hung
Filed: 3 Aug 23
Utility
xnkrw48sjxzwo85hib46jr3c6ynwsj
7 Dec 23
Systems, methods, and devices are described herein for generating a pulse width modulation (PWM) signal having a specific duty cycle.
Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
Filed: 8 Aug 23
Utility
plxtet06n2xv4icxsv32n0ucttrvjp35euri3xfw7p
7 Dec 23
A semiconductor device includes an input, a level shifter, an output, and a switch module.
Jerrin Pathrose Vareed, Shiba Mohanty
Filed: 10 Aug 23
Utility
e70v01vnymhmk13k39m2nydhlhjgouo6zd2bxq6wzw5b6ekg
7 Dec 23
A method and system for authenticating a device is provided.
Robert Abbott, Saman M.I. Adham, Peter Noel
Filed: 10 Aug 23
Utility
u0ayy4dg7y43wh333yei39vg8lm7m83j4h1g
7 Dec 23
A memory device is provided in various embodiments.
Hung-Ju Li, Kuo-Pin Chang, Yu-Wei Ting, Ching-En Chen, Kuo-Ching Huang
Filed: 7 Jun 22
Utility
10ny4nxe4 6kt5s68ryjw4lbqkfepcot3am5lm9d8co098u7bsqtlwa
7 Dec 23
A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor.
Chenchen Wang, Chun-Chieh Lu, Chi On Chui, Yu-Ming Lin, Sai-Hooi Yeong
Filed: 10 Aug 23
Utility
krjkl2zuiopj3qpauc drv2
7 Dec 23
Integrated circuit (IC) chips and seal ring structures are provided.
Chun Yu Chen, Yen Lian Lai
Filed: 20 Jul 23
Utility
5jsymywkktd0f7louyga
7 Dec 23
A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
Huei-Tsz WANG, Po-Shu WANG, Wei-Ming WANG
Filed: 10 Aug 23
Utility
g6guemhum8brmx0ycwjnaumn3fnfiddk7sz
7 Dec 23
Systems and methods are provided for monitoring wafer bonding and for detecting or determining defects in a wafer bond formed between two semiconductor wafers.
Chih-Yu WANG, Hsi-Cheng HSU
Filed: 11 Aug 23