28912 patents
Page 41 of 1446
Utility
Metal Gates for Multi-gate Semiconductor Devices and Method Thereof
7 Dec 23
A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks.
Chih-Wei Lee, Jo-Chun Hung, Wen-Hung Huang, Jian-Hao Chen, Kuo-Feng Yu
Filed: 5 Jun 22
Utility
Integrated Packages Having Electrical Devices and Photonic Devices and Methods of Manufacturing the Same
7 Dec 23
A semiconductor package includes a photonic die having a first side and a second side opposite to each other.
Chan-Hong Chern
Filed: 7 Jun 22
Utility
Semiconductor Device and Method Forming Same
7 Dec 23
Package structures and methods of forming package structures are discussed.
Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chien-Li Kuo, Kuo-Chio Liu
Filed: 6 Jun 22
Utility
Insulating Structures In Semiconductor Device
7 Dec 23
The present disclosure describes a structure that provides insulation in a semiconductor device and a method for forming the structure.
Tzu-Ging LIN, Chen-Yu Tai
Filed: 3 Jun 22
Utility
Bilayer RDL Structure for Bump Count Reduction
7 Dec 23
A method of forming semiconductor device includes forming interconnect structure over substrate; forming first passivation layer over the interconnect structure, and metal-insulator-metal capacitor in the first passivation layer; forming first redistribution layer including first pads over the first passivation layer, and first vias extending into the first passivation layer; conformally forming second passivation layer over the first redistribution layer and first passivation layer, and patterning the second passivation layer to form via openings exposing the first pads; forming second redistribution layer including second pads over the second passivation layer, and second vias in the first via openings, wherein the first and second redistribution layers include aluminum-copper alloy and copper, respectively; forming dielectric layer over the second redistribution layer, and patterning the dielectric layer to form via openings exposing some second pads; and forming bumps over the dielectric layer and in the via openings to contact exposed second pads.
Tsung-Chieh HSIAO, Liang-Wei WANG, Dian-Hau CHEN
Filed: 1 Jun 22
Utility
Nanostructured Channel Regions for Semiconductor Devices
7 Dec 23
A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed.
Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG, Perng-Fei YUH
Filed: 8 Aug 23
Utility
3D Stacking Architecture Through TSV and Methods Forming Same
7 Dec 23
A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer.
Hsien-Wei Chen, Jie Chen, Shin-Puu Jeng
Filed: 2 Jun 22
Utility
Semiconductor Device and Manufacturing Method Thereof
7 Dec 23
A method includes forming a semiconductor structure on a substrate; performing a first etching process on the semiconductor structure to form a fin structure upwardly extending above the substrate; performing a second etching process to trim the fin structure to have a reverse-trapezoidal cross-sectional profile; forming source/drain regions on opposite regions of the fin structure; forming a gate structure between the source/drain regions.
Chien-Te TU, Chee-Wee LIU
Filed: 1 Jun 22
Utility
Semiconductor Structures With Improved Reliability
7 Dec 23
Semiconductor structures and methods are provided.
Kuei-Ming Chen, Chi-Ming Chen, Shih-Pang Chang
Filed: 3 Jun 22
Utility
Heterostructure Channel Layer for Semiconductor Devices
7 Dec 23
The present disclosure describes a semiconductor structure having a heterostructure channel layer.
W.Y. LIN, H.S. Hu, Chao-Chi Chen
Filed: 6 Jun 22
Utility
Semiconductor Package with Improved Heat Distribution
7 Dec 23
A semiconductor structure and processes of forming the same are provided.
Tsung-Chieh Hsiao, Chih Hsin Yang, Liang-Wei Wang, Dian-Hau Chen
Filed: 2 Jun 22
Utility
Semiconductor Device and Formation Method Thereof
7 Dec 23
A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.
Chia-Che CHUNG, Chia-Jung TSEN, Chee-Wee LIU
Filed: 7 Jun 22
Utility
Semiconductor Device Structure Including Forksheet Transistors and Methods of Forming the Same
7 Dec 23
A method for forming a semiconductor device structure includes forming first, second, and third fin structures from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers, the second fin structure includes a second plurality of semiconductor layers, and the third fin structure includes a third plurality of semiconductor layers, and wherein each of the first, second, and third plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers.
Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
Filed: 4 Aug 23
Utility
Power Rails For Stacked Semiconductor Device
7 Dec 23
The present disclosure describes a method to form a stacked semiconductor device with power rails.
Chansyun David YANG, Keh-Jeng Chang, Chan-Lon Yang
Filed: 10 Aug 23
Utility
Method of Making Semiconductor Device Having Buried Bias Pad
7 Dec 23
A method of making a semiconductor device includes manufacturing a bias layer over a buried oxide layer.
Jian WU, Feng HAN, Shuai ZHANG
Filed: 10 Aug 23
Utility
Capacitor and Method for Forming the Same
7 Dec 23
The method includes forming a sacrificial multi-layer stack including alternating first sacrificial layers and second sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layers to form first spaces each interposing two of the second sacrificial layers; depositing a first dielectric layer and a first electrode material in the first spaces; removing the second sacrificial layers to form second spaces each interposing two portions of the first electrode material; depositing a second dielectric layer and a second electrode material in the second spaces.
Hsin-Cheng LIN, Chia-Che CHUNG, Chee-Wee LIU
Filed: 1 Jun 22
Utility
Semiconductor Devices and Methods of Fabrication Thereof
7 Dec 23
A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature.
Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Chung CHIU, Ke-Chia TSENG, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
Filed: 2 Jun 22
Utility
Semiconductor Device and Method of Forming the Same
7 Dec 23
Provided are a semiconductor device and a method of forming the same.
Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien-Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
Filed: 5 Jun 22
Utility
Multilayer Masking Layer and Method of Forming Same
7 Dec 23
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
Filed: 2 Aug 23
Utility
Semiconductor Device and Method for Forming the Same
7 Dec 23
A method includes forming a first semiconductor layer over a substrate; forming a dummy material covering a first sidewall of the first semiconductor layer; forming source/drain epitaxy structures over the substrate and in contact with the first semiconductor layer; forming an interfacial layer on a top surface and a second sidewall of the first semiconductor layer that are uncovered by the dummy material; removing the dummy material to expose the first sidewall of the first semiconductor layer; forming a second semiconductor layer on the first sidewall of the first semiconductor layer after removing the dummy material, in which the second semiconductor layer and the source/drain epitaxy structures have different conductivity types; and forming a gate electrode over the interfacial layer.
Chih-Hao WANG, Ching-Wei TSAI, Yu-Xuan HUANG
Filed: 2 Jun 22