28912 patents
Page 38 of 1446
Utility
Method for mask data synthesis with wafer target adjustment
12 Dec 23
A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout.
Hsu-Ting Huang, Tung-Chin Wu, Shih-Hsiang Lo, Chih-Ming Lai, Jue-Chin Yu, Ru-Gun Liu, Chin-Hsiang Lin
Filed: 16 Aug 21
Utility
Package assembly and manufacturing method thereof
12 Dec 23
A package assembly and a manufacturing method thereof are provided.
Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
Filed: 26 May 20
Utility
Photoresist system and method
12 Dec 23
A photoresist apparatus and a method are provided.
Hung-Jui Kuo, De-Yuan Lu, Chen-Hua Yu, Ming-Tan Lee
Filed: 3 Jan 22
Utility
Method and apparatus for diffraction-based overlay measurement
12 Dec 23
A method of overlay error measurement includes disposing a reference pattern module over a substrate.
Hung-Chih Hsieh, Yen-Liang Chen
Filed: 14 Mar 22
Utility
Integrated circuit and method of manufacturing same
12 Dec 23
An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via.
Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Shun Li Chen, Wei-Cheng Lin
Filed: 19 Aug 21
Utility
Method and system for determining equivalence of design rule manual data and design rule checking data
12 Dec 23
The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set.
Chin-Chou Liu, Yi-Kuang Lee, Lie-Szu Juang
Filed: 3 Aug 21
Utility
Integrated circuit layout generation method and system
12 Dec 23
A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region.
Ke-Ying Su, Ke-Wei Su, Keng-Hua Kuo, Lester Chang
Filed: 24 Sep 20
Utility
Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells
12 Dec 23
A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium.
Mao-Wei Chiu, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Chi-Yu Lu
Filed: 5 Apr 21
Utility
Defect offset correction
12 Dec 23
A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
Filed: 4 Aug 22
Utility
Layout structures of memory array and related methods
12 Dec 23
A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.
Meng-Sheng Chang, Yao-Jen Yang, Shao-Yu Chou, Yih Wang
Filed: 3 Jan 22
Utility
Crystal seed layer for magnetic random access memory (MRAM)
12 Dec 23
Some embodiments relate to a memory device.
Tsann Lin, Ji-Feng Ying, Chih-Chung Lai
Filed: 8 Dec 22
Utility
Semiconductor package with alignment mark and manufacturing method thereof
12 Dec 23
A semiconductor package includes a die and an encapsulant.
Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
Filed: 2 May 21
Utility
Dual etch-stop layer structure
12 Dec 23
The present disclosure relates to an integrated chip including a substrate.
Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee
Filed: 3 Jun 21
Utility
In-situ formation of metal gate modulators
12 Dec 23
A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer.
Hsin-Han Tsai, Chung-Chiang Wu, Cheng-Lung Hung, Weng Chang, Chi On Chui
Filed: 30 Jun 22
Utility
Method for forming a reconstructed package substrate comprising substrates blocks
12 Dec 23
A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant.
Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
Filed: 12 May 21
Utility
Integrated chip with inter-wire cavities
12 Dec 23
The present disclosure relates to an integrated chip comprising a substrate.
Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Yen Huang, Chia-Tien Wu
Filed: 23 Jun 21
Utility
Semiconductor structure
12 Dec 23
The semiconductor structure includes a plurality of first dies, a plurality of second dies disposed over each of the first dies, and a dielectric material surrounding the plurality of first dies and the plurality of second die.
Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Tien-Chung Yang
Filed: 12 Nov 21
Utility
Semiconductor device and method
12 Dec 23
In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.
Tsai-Yu Huang, Han-De Chen, Huicheng Chang, Yee-Chia Yeo
Filed: 15 Jan 21
Utility
Underfill structure for semiconductor packages and methods of forming the same
12 Dec 23
A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed.
Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
Filed: 26 Jul 21
Utility
Semiconductor package having an encapsulant comprising conductive fillers and method of manufacture
12 Dec 23
Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed.
Xinyu Bao, Lee-Chung Lu, Jyh Chwen Frank Lee, Fong-yuan Chang, Sam Vaziri, Po-Hsiang Huang
Filed: 2 Aug 21