28912 patents
Page 36 of 1446
Utility
Integration of Solar Cell and Image Sensor
14 Dec 23
The present disclosure provides an integrated circuit (IC) structure with a solar cell and an image sensor array.
Feng-Chien Hsieh, Yun-Wei Cheng, Ping Kuan Chang, Kuo-Cheng Lee, Cheng-Ming Wu
Filed: 22 Aug 22
Utility
Semiconductor Device Structure and Methods of Forming the Same
14 Dec 23
A semiconductor device structure, along with methods of forming such, are described.
Tzu-Ging LIN, Chen-Yu TAI, Chun-Liang LAI, Chih-Chang HUNG
Filed: 10 Jun 22
Utility
Cascaded Bipolar Junction Transistor and Methods of Forming the Same
14 Dec 23
A device and methods of forming the same are described.
Hong-Shyang WU, Kuo-Ming WU
Filed: 13 Jun 22
Utility
Systems and Methods for Suppressing and Mitigating Harmonic Distortion In a Circuit
14 Dec 23
Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed.
Feng-Wei KUO, Kai XU, Robert Bogdan STASZEWSKI
Filed: 9 Aug 23
Utility
Heterogenous Bonding Layers for Direct Semiconductor Bonding
14 Dec 23
A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers.
Kuang-Wei CHENG, Chyi-Tsong NI
Filed: 10 Aug 23
Utility
Integrated Standard Cell Structure
14 Dec 23
An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction.
Shih-Hsien Huang, Cheng-Hua Liu, Kuang-Hung Chang, Sheng-Hsiung Wang, Chun-Yen Lin, TUNG-HENG HSIEH, BAO-RU Young
Filed: 10 Jun 22
Utility
Integrated Circuit Layout Method
14 Dec 23
A method of generating an IC layout diagram includes positioning a resistor unit cell in the IC layout diagram, a resistor of the resistor unit cell including a source/drain metal region, positioning a MOS unit cell in the IC layout diagram, overlapping the resistor unit cell with a first via region, overlapping the MOS unit cell with a second via region, overlapping the first and second via regions with a continuous conductive region, and storing the IC layout diagram in a storage device.
Po-Zeng KANG, Wen-Shen CHOU, Yung-Chow PENG
Filed: 10 Aug 23
Utility
Semiconductor Device Structure and Methods of Forming the Same
14 Dec 23
A semiconductor device structure, along with methods of forming such, are described.
Ya-Yi TSAI, Sheng-Yi Hsiao, Shu-Yuan KU, Ryan Chia-Jen CHEN, Tzu-Ging LIN, Jih-Jse LIN, Yih-Ann LIN
Filed: 15 Jan 23
Utility
Apparatus and Methods for Sensing Long Wavelength Light
14 Dec 23
Apparatus and methods for sensing long wavelength light are described herein.
Yun-Wei CHENG, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
Filed: 9 Aug 23
Utility
Field Effect Transistor with Gate Isolation Structure and Method
14 Dec 23
A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures.
Kuo-Cheng CHIANG, Guan-Lin CHEN, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG
Filed: 2 Feb 23
Utility
Forming Integrated Electronic Devices for Converting and Downscaling Alternating Current
14 Dec 23
Bonding a full-bridge device and an LLC device in a stack, or forming the full-bridge device and the LLC device on a same substrate, rather than connecting the devices, reduces a chip area associated with a power converter including the full-bridge device and the LLC device.
Yen-Ku LIN, Ru-Yi SU, Haw-Yun WU, Chun-Lin TSAI
Filed: 13 Jun 22
Utility
Magneto-resistive Random-access Memory (Mram) Devices and Methods of Forming the Same
14 Dec 23
Embodiments of the present disclosure provide a magnetic tunnel junction (MTJ) structure for storing a data.
Hsuan-Yi PENG, Cherng-Yu WANG, Jen-Po LIN, Hsiao-Kuan WEI
Filed: 12 Jun 22
Utility
Embedded Ferroelectric Finfet Memory Device
14 Dec 23
Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device.
Bo-Feng Young, Chung-Te Lin, Sai-Hooi Yeong, Yu-Ming Lin, Sheng-Chih Lai, Chih-Yu Chang, Han-Jong Chia
Filed: 3 Aug 23
Utility
Phase-change Random Access Memory Device and Method of Forming the Same
14 Dec 23
Various embodiments of the present disclosure provide a memory device and methods of forming the same.
Chin I WANG, Huan-Chieh CHEN, Chia-Wen ZHONG, Yao-Wen CHANG
Filed: 11 Jun 22
Utility
Wafer Level Multi-Die Structure Formation
14 Dec 23
An array of dies is formed over a substrate.
Shan-Yu Huang, Shih-Chang Chen, Yilun Chen, Huang-Sheng Lin
Filed: 14 Jun 22
Utility
Integrated Circuit, System and Method of Forming the Same
14 Dec 23
An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop.
Te-Hsin CHIU, Wei-Cheng LIN, Wei-An LAI, Jiann-Tyng TZENG
Filed: 10 Aug 23
Utility
Method of Manufacturing Semiconductor Image Sensor
14 Dec 23
A method of manufacturing a semiconductor device includes disposing a plurality of a first type of light sensing units on a substrate; and disposing a plurality of a second type of light sensing units arranged on the substrate.
Li-Wen HUANG, Chung-Lin FANG, Kuan-Ling PAN, Ping-Hao LIN, Kuo-Cheng LEE, Cheng-Ming WU
Filed: 10 Aug 23
Utility
Reduced Cross-talk In Color and Infrared Image Sensor
14 Dec 23
Various embodiments of the present disclosure are directed towards an image sensor device including a first image sensor element and a second image sensor element disposed within a substrate.
Keng-Yu Chou, Cheng Yu Huang, Chun-Hao Chuang, Wen-Hau Wu, Wei-Chieh Chiang, Wen-Chien Yu, Chih-Kung Chang
Filed: 8 Aug 23
Utility
Deep Trench Isolation Structure and Methods for Fabrication Thereof
14 Dec 23
A Deep Trench Isolation (DTI) structure is disclosed.
Bi-Shen LEE, Chia-Wei HU, Hai-Dang TRINH, Min-Ying TSAI, Ching I LI, Hsun-Chung KUANG, Cheng-Yuan TSAI
Filed: 13 Jun 22
Utility
Integrated Circuit with Feol Resistor
14 Dec 23
A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region, forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region, forming first source/drain regions in the active region and second source/drain regions in the passive region, after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate, forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure, and electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts.
Tien-Chien HUANG, Ruey-Bin SHEEN, Chih-Hsien CHANG
Filed: 10 Aug 23