28912 patents
Page 32 of 1446
Utility
System, device and methods of manufacture
19 Dec 23
Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein.
Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Tin-Hao Kuo, Che-Wei Hsu
Filed: 21 Jul 22
Utility
Semiconductor structure and related methods
19 Dec 23
Methods and associated devices including the fabrication of a semiconductor structure are described that include epitaxially growing a stack of layers alternating between a first composition and a second composition.
Hung-Jiu Chou, Yuan-Ching Peng, Jiun-Ming Kuo
Filed: 9 May 22
Utility
Integrated circuit package and method
19 Dec 23
In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.
Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh
Filed: 7 May 21
Utility
Redistribution layer structures for integrated circuit package
19 Dec 23
A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed.
Jie Chen, Ying-Ju Chen, Hsien-Wei Chen, Der-Chyang Yeh, Chen-Hua Yu
Filed: 2 Jul 21
Utility
Semiconductor device for providing spike voltage protection and manufacturing method thereof
19 Dec 23
A semiconductor device is provided.
Hong-Shyang Wu, Kuo-Ming Wu
Filed: 23 Apr 21
Utility
Semiconductor structure with self-aligned backside power rail
19 Dec 23
The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.
Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
Filed: 25 Jul 22
Utility
Semiconductor device and manufacturing method thereof
19 Dec 23
A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate.
Gao-Ming Wu, Katherine H. Chiang, Chien-Hao Huang, Chung-Te Lin
Filed: 23 Jul 21
Utility
Method for manufacturing semiconductor device
19 Dec 23
A method for manufacturing a semiconductor device is provided.
Bo-Wen Hsieh, Wen-Hsin Chan
Filed: 21 May 21
Utility
Transistors with different threshold voltages
19 Dec 23
A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided.
Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang
Filed: 18 Oct 21
Utility
Semiconductor devices and methods of manufacture
19 Dec 23
A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell.
Wei-Chih Kao, Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
Filed: 21 Jun 21
Utility
Methods of operating multi-bit memory storage device
19 Dec 23
A method (of reading a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes reading the second bit including: applying a gate sub-threshold voltage to the gate terminal; applying a read voltage to the second S/D terminal; applying a do-not-disturb voltage to the first S/D terminal; and sensing a first current at the second S/D terminal; and wherein the read voltage is lower than the do-not-disturb voltage.
Meng-Han Lin, Chia-En Huang, Han-Jong Chia, Martin Liu, Sai-Hooi Yeong, Yih Wang
Filed: 22 Jul 22
Utility
Method for forming semiconductor device structure
19 Dec 23
A method for forming a semiconductor device structure is provided.
Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
Filed: 9 Aug 22
Utility
Semiconductor package and manufacturing method thereof
19 Dec 23
A method includes the following steps.
Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
Filed: 27 Mar 22
Utility
Functional component within interconnect structure of semiconductor device and method of forming same
19 Dec 23
A semiconductor device includes a substrate.
Hsien-Wei Chen, Ming-Fa Chen
Filed: 22 Nov 21
Utility
Chip structure and method for forming the same
19 Dec 23
A chip structure is provided.
Hong-Seng Shue, Sheng-Han Tsai, Kuo-Chin Chang, Mirng-Ji Lii, Kuo-Ching Hsu
Filed: 25 May 19
Utility
Image sensor with passivation layer for dark current reduction
19 Dec 23
Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction.
Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
Filed: 17 Feb 21
Utility
Semiconductor device structure with source/drain structure
19 Dec 23
A semiconductor device structure is provided.
Tung-Ying Lee, Kai-Tai Chang
Filed: 6 Jun 22
Utility
Charged Particle Filter and Removal System
14 Dec 23
The present disclosure is directed to at least one embodiment of a filter that is configured to remove contaminants utilizing a first conductive mesh (e.g., first electrode) and a second conductive mesh (e.g., second electrode) that extends around the first conductive mesh.
En Tian LIN, Chiao Ling WENG
Filed: 13 Jun 22
Utility
Lithography System and Method Thereof
14 Dec 23
A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film.
Shao-Hua WANG, Chueh-Chi KUO, Kuei-Lin HO, Zong-You YANG, Cheng-Wei SUN, Wei-Yuan CHEN, Cheng-Chieh CHEN, Heng-Hsin LIU, Li-Jui CHEN
Filed: 28 Jul 23
Utility
Micro-electromechanical Systems (Mems) Device with Outgas Layer
14 Dec 23
The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate.
Fan Hu, Wen-Chuan Tai, Li-Chun Peng, Hsiang-Fu Chen, Ching-Kai Shen, Hung-Wei Liang, Jung-Kuo Tu
Filed: 8 Jun 22