28912 patents
Page 35 of 1446
Utility
Image Sensor
14 Dec 23
The present disclosure describes a three-chip complementary metal-oxide-semiconductor (CMOS) image sensor and a method for forming the image sensor.
Chun-Hao CHUANG, Keng-Yu CHOU, Cheng Yu HUANG, Wen-Hau WU, Wei-Chieh CHIANG, Chih-Kung CHANG, Tzu-Hsuan HSU
Filed: 10 Jun 22
Utility
Double Patterning Techniques for Forming a Deep Trench Isolation Structure
14 Dec 23
Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array.
Wei-Chao CHIU, Yu-Wen CHEN, Yong-Jin LIOU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
Filed: 10 Aug 23
Utility
Image Sensor with High Quantum Efficiency
14 Dec 23
The present disclosure describes an image sensor device and a method for forming the same.
Feng-Chien HSIEH, Hsin-Chi Chen, Kuo-Cheng Lee, Yun-Wei Cheng
Filed: 10 Aug 23
Utility
Dicing Method for Stacked Semiconductor Devices
14 Dec 23
A semiconductor structure includes a first device and a second device bonded on the first device.
Tsung-Hsing Lu, Jun He, Li-Huan Chu, Pei-Haw Tsao
Filed: 10 Aug 23
Utility
Semiconductor Device with Dielectric Liners on Gate Refill Metal
14 Dec 23
A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner.
Yuan-Hsiang WU, Jia-Chuan YOU, Chia-Hao CHANG, Kuo-Cheng CHIANG, Chih-Hao WANG
Filed: 10 Jun 22
Utility
Heat Dissipation Structures for Integrated Circuit Packages and Methods of Forming the Same
14 Dec 23
A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, where the ring surrounds the first die and the interposer, a molding compound disposed between the ring and the first die, where the molding compound is in physical contact with the ring, and a plurality of thermal-conductive layers over and in physical contact with the molding compound and the first die, where the molding compound is disposed between the plurality of thermal-conductive layers and the ring.
Szu-Wei Lu, Tsung-Fu Tsai, Chi-Hsiang Chen
Filed: 10 Jun 22
Utility
Semiconductor Device Structure and Method for Forming the Same
14 Dec 23
A method for forming a semiconductor device structure includes forming a gate structure surrounding the nanostructures.
Li-Zhen YU, Lin-Yu HUANG, Huan-Chieh SU
Filed: 13 Jun 22
Utility
Signal Conducting Line Arrangements In Integrated Circuits
14 Dec 23
A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure.
Wei-Ling CHANG, Chih-Liang CHEN, Chia-Tien WU, Guo-Huei WU
Filed: 10 Aug 23
Utility
Fin Field Effect Transistor and Manufacturing Method Thereof
14 Dec 23
A FinFET includes a semiconductor substrate, a semiconductor fin, a gate structure, and an isolation structure.
Ya-Yi Tsai, Sheng-Yi Hsiao, Chao-Hsuan Chen, Yun-Ting Chiang, Shu-Yuan Ku
Filed: 13 Jun 22
Utility
Heat Controlled Switch
14 Dec 23
A semiconductor device is disclosed.
Yu-Wei Ting, Kuo-Pin Chang, Hung-Ju Li, Kuo-Ching Huang
Filed: 8 Jun 22
Utility
Semiconductor Memory Devices and Methods of Manufacturing Thereof
14 Dec 23
A semiconductor device includes a memory structure comprising a plurality of first memory cells.
Meng-Han Lin, Chia-En Huang, Sai-Hooi Yeong
Filed: 8 Jun 22
Utility
Semiconductor Device and Methods of Manufacturing
14 Dec 23
In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first t
Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
Filed: 8 Aug 23
Utility
Ferroelectric Tunnel Junction Memory Devices with Enhanced Read Window
14 Dec 23
A semiconductor device includes a first capacitor having a ferroelectric film disposed between two electrodes, a second capacitor, having another dielectric film disposed between two electrodes.
Wei Ting HSIEH, Kuen-Yi CHEN, Yi-Hsuan CHEN, Yu-Wei TING, Yi Ching ONG, Kuo-Ching HUANG
Filed: 14 Jun 22
Utility
Mid-manufacturing Semiconductor Wafer Layer Testing
14 Dec 23
A method of manufacturing a semiconductor wafer is disclosed.
Feng-Chien Hsieh, Kuo-Cheng Lee, Yun-Wei Cheng, Chun-Hao Lin, Ting-Hao Chang
Filed: 7 Aug 23
Utility
Semiconductor Devices
14 Dec 23
A semiconductor device includes a first electrode layer, a ferroelectric layer, and a second electrode layer.
Ying-Chih Chen, Blanka Magyari-Kope
Filed: 9 Jun 22
Utility
Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures
14 Dec 23
A first die includes a plurality of first transistors.
Shan-Yu Huang, Yilun Chen, Huang-Sheng Lin
Filed: 13 Jun 22
Utility
Molding Structures for Integrated Circuit Packages and Methods of Forming the Same
14 Dec 23
In an embodiment, a method of forming a semiconductor device includes: attaching an integrated circuit die to an interposer; forming an encapsulant over the interposer and around the integrated circuit die, a top surface of the encapsulant and a top surface of the integrated circuit die being level; forming recesses in the encapsulant; and bonding the interposer to a package substrate, wherein after bonding the interposer to the package substrate, each of the recesses being along an outer edge of the encapsulant.
Shu-Shen Yeh, Chin-Hua Wang, Chipta Priya Laksana, Po-Yao Lin, Shin-Puu Jeng
Filed: 14 Jun 22
Utility
Semiconductor Package and Method of Manufacturing
14 Dec 23
Some implementations described herein provide a semiconductor package including an integrated circuit die mounted to an interposer using connection structures.
Chien LI, Chih-Ju YEN, Jui Hsien LO, Chien-Sheng CHEN, Shin-Puu JENG
Filed: 10 Jun 22
Utility
Semiconductor Device and Method of Operating Same
14 Dec 23
A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks.
Liu HAN, Xin Yong WANG, Qingchao MENG, Huaixin XIAN, Jing DING
Filed: 10 Aug 23
Utility
Pixel Sensor Including Refraction Structures
14 Dec 23
A pixel sensor may include a main deep trench isolation (DTI) structure and one or more sub-DTI structures in a substrate of the pixel sensor to increase the quantum efficiency of the pixel sensor at large incident angles.
Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
Filed: 7 Aug 23