28912 patents
Page 28 of 1446
Utility
Integrated Circuit and Manufacturing Method Thereof
21 Dec 23
An integrated circuit includes a substrate, a first transistor, and an interconnect structure.
Katherine H CHIANG, Chung-Te Lin
Filed: 19 Jun 22
Utility
Dielectric Blocking Layer and Method Forming the Same
21 Dec 23
A method includes forming a first package component, which comprises forming a first dielectric layer having a first top surface, and forming a first conductive feature.
Chih-Wei Wu, Ying-Ching Shih, Wen-Chih Chiou
Filed: 1 Sep 22
Utility
Spacer Stack For Magnetic Tunnel Junctions
21 Dec 23
The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers.
Joung-Wei LIOU, Chin Kun LAN
Filed: 31 Jul 23
Utility
Integrated Circuit and Method of Forming the Same
21 Dec 23
An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer.
Kuang-Ching CHANG, Jung-Chan YANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Kuo-Nan YANG
Filed: 1 Aug 23
Utility
Electrostatic Discharge Protection Device and Method of Making
21 Dec 23
A semiconductor device includes a substrate.
Tzu-Hao CHIANG, Wun-Jie LIN, Jam-Wem LEE
Filed: 27 Jul 23
Utility
Semiconductor Device Having Nanosheets
21 Dec 23
Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.
Te-Hsin CHIU, Kam-Tou SIO, Shang-Wei FANG, Wei-Cheng LIN, Jiann-Tyng TZENG
Filed: 10 Aug 23
Utility
Integrated Circuit Structure and Method with Hybrid Orientation for FinFET
21 Dec 23
The present disclosure provides a semiconductor structure.
Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
Filed: 20 Jul 23
Utility
Light Absorbing Layer to Enhance P-type Diffusion for Dti In Image Sensors
21 Dec 23
In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.
Yu-Hung Cheng, Ching I Li, Yu-Siang Fang, Yu-Yao Hsia, Min-Ying Tsai
Filed: 3 Aug 23
Utility
Stacked Cmos Image Sensor and Method of Manufacturing the Same
21 Dec 23
Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor with a high full well capacity (FWC).
Chi-Hsien Chung, Tzu-Jui Wang, Chen-Jong Wang, Tzu-Hsuan Hsu, Dun-Nian Yaung
Filed: 15 Aug 22
Utility
Package with Permalloy Core Inductor and Manufacturing Method Thereof
21 Dec 23
A package includes a first redistribution structure, a die disposed over the first redistribution structure, a molding material surrounding the die, a second redistribution structure over the die and the molding material, and an inductor includes a permalloy core.
Wen-Shiang Liao
Filed: 20 Jun 22
Utility
Semiconductor Device and Methods of Formation
21 Dec 23
Some implementations described herein provide a semiconductor device having an oxide-filled barrier structure between structures of gate-all-around transistors included in the semiconductor device.
Cheng-Wei CHANG, Shahaji B. MORE, Chi-Yu CHOU, Yueh-Ching PAI
Filed: 27 May 22
Utility
Semiconductor Device and Methods of Formation
21 Dec 23
Some implementations described herein include a semiconductor device including a gate-all-around transistor.
Shahaji B. MORE
Filed: 16 Jun 22
Utility
Semiconductor Device and Method
21 Dec 23
Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed.
Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
Filed: 7 Aug 23
Utility
Method of Manufacturing a Semiconductor Device and a Semiconductor Device
21 Dec 23
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed.
Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
Filed: 25 May 22
Utility
Methods of Manufacturing Semiconductor Devices and Semiconductor Devices
21 Dec 23
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space.
Che-Lun CHANG, Kuan-Ting PAN, Wei-Yang LEE, Chia-Pin LIN
Filed: 16 Jun 22
Utility
Transistor Gate Structures and Methods of Forming the Same
21 Dec 23
In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.
Shih-Yao Lin, Chen-Ping Chen, Hsiaowen Lee, Chih-Han Lin
Filed: 2 Aug 23
Utility
Semiconductor Device and Manufacturing Method Thereof
21 Dec 23
In a method of manufacturing a semiconductor device, a FET structure is formed over a substrate, which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, a gate electrode disposed over the gate dielectric layer and a source/drain structure.
Chih-Hao WANG, Chun-Yuan CHEN, Huan-Chieh SU, Sheng-Tsung WANG, Lo-Heng CHANG, Kuo-Cheng CHIANG
Filed: 18 Aug 22
Utility
Isolation Regions with Non-Uniform Depths and Methods Forming the Same
21 Dec 23
A method includes forming a plurality of semiconductor structures over a semiconductor substrate, forming a dummy gate stack on top surfaces and sidewalls of the plurality of semiconductor structures, forming gate spacers on sidewalls of the dummy gate stack, and etching a first portion of the dummy gate stack to form a through-gate trench in the dummy gate stack.
Tzu-Ging Lin
Filed: 6 Jan 23
Utility
High Aspect Ratio Gate Structure Formation
21 Dec 23
A method includes forming a fin over a substrate, forming an isolation structure on the substrate, and forming first and second mandrel patterns over the fin.
Sai-Hooi Yeong, Chi-On Chui, Kai-Hsuan Lee, Kuan-Lun Cheng, Chih-Hao Wang
Filed: 8 Aug 23
Utility
Semiconductor Device Structure and Method for Forming the Same
21 Dec 23
A semiconductor structure and method of forming a semiconductor structure are provided.
Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Yi-Ning TAI, Hong-Mao LEE, Yan-Ming TSAI, Wei-Yip LOH, Harry CHIEN, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
Filed: 23 May 22