28912 patents
Page 26 of 1446
Utility
Three Dimensional Integrated Circuit and Fabrication Thereof
21 Dec 23
An IC structure includes a first transistor, a dielectric layer, a plurality of semiconductor pillars, a plurality of semiconductor plugs, a semiconductor structure, and a second transistor.
Chenming HU, Kuan-Neng CHEN, Po-Tsang HUANG, Hao-Tung CHUNG, Bo-Jheng SHIH, Yu-Ming PAN
Filed: 17 Jun 22
Utility
Cyclic Spin-On Coating Process for Forming Dielectric Material
21 Dec 23
The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices.
Je-Ming Kuo, Yen-Chun Huang, Chih-Tang Peng, Tien-I Bao
Filed: 31 Jul 23
Utility
Core-Shell Nanostructures For Semiconductor Devices
21 Dec 23
The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed.
Cheng-Yi Peng, Song-Bor Lee
Filed: 9 Aug 23
Utility
Method of Making Cell Regions of Integrated Circuits
21 Dec 23
A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell.
Jia-Hong GAO, Hui-Zhong ZHUANG
Filed: 10 Aug 23
Utility
Structure and Formation Method of Semiconductor Device with Gate Stack
21 Dec 23
A semiconductor device structure and a formation method are provided.
Chun-Yi CHANG, Wen-Li CHIU, Hsin-Che CHIANG, Chun-Sheng LIANG
Filed: 15 Jun 22
Utility
Automated Material Handling System for Use In Power Outage Recovery
21 Dec 23
When there is an interruption in power to an area of an integrated circuit manufacturing facility, product may be stranded in a vehicle mounted to an automated material handling system.
Chun-Jung HUANG, Y.Y. LEE, Kuang Huan HSU, Li-Hsin CHU, Jen-Ti WANG, Chieh HSU
Filed: 17 Jun 22
Utility
Semiconductor Device and Manufacturing Method Thereof
21 Dec 23
A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a sidewall spacer.
Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien Ning YAO, Tsung-Han CHUANG, Kai-Lin CHUANG, Kuo-Cheng CHIANG
Filed: 17 Jun 22
Utility
Semiconductor Processing Tool and Methods of Operation
21 Dec 23
Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold.
I-Nan. CHEN, Kuo-Ming WU, Ming-Che LEE, Hau-Yi HSIAO, Yung-Lung LIN, Che Wei YANG, Sheng-Chau CHEN
Filed: 17 Jun 22
Utility
Method for Improving Profile of Interconnect Structure
21 Dec 23
A method for manufacturing a semiconductor device includes: forming a patterned dielectric layer over a substrate, the patterned dielectric layer including an interconnect opening having a sidewall surface and a bottom surface; and forming a doped film by an opening-adjustment process, the doped film being disposed on the patterned dielectric layer and extending into the interconnect opening to cover an upper portion of the sidewall surface, so as to adjust a profile of the interconnect opening.
Chun-Neng LIN, Jian-Jou LIAN, Chieh-Wei CHEN
Filed: 16 Jun 22
Utility
Semiconductor Device Structure and Methods of Forming the Same
21 Dec 23
A semiconductor device structure, along with methods of forming such, are described.
Liang-Hsuan PENG, Chih-Hung LU, Chih-Lin WANG, Song-Bor LEE
Filed: 21 Jun 22
Utility
Interconnect Structure and Method of Forming the Same
21 Dec 23
Provided are an interconnect structure and a method of forming the same.
Ming-Yang Li, Chih-Piao Chuu, Szuya Liao, Han Wang
Filed: 17 Jun 22
Utility
Semiconductor Device and Method
21 Dec 23
Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed.
Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
Filed: 7 Aug 23
Utility
Semiconductor Device and Method for Forming the Same
21 Dec 23
A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.
Po-Hsien CHENG, Zhen-Cheng WU
Filed: 21 Jun 22
Utility
Integrated Circuit Structure and Method with Hybrid Orientation for FinFET
21 Dec 23
The present disclosure provides a semiconductor structure.
Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
Filed: 20 Jul 23
Utility
Embedded Capacitors with Shared Electrodes
21 Dec 23
Capacitors and interconnect structures that couple transistors to one another include parallel stacked metal lines separated by dielectric layers.
Meng-Hsien Lin, Hsing-Chih Lin, Ke Chun Liu, Min-Feng Kao, Kuan-Hua Lin
Filed: 17 Jun 22
Utility
Semiconductor Device and Methods of Formation
21 Dec 23
Some implementations described herein include a semiconductor device including a gate-all-around transistor.
Shahaji B. MORE
Filed: 16 Jun 22
Utility
Semiconductor Device and Method of Manufacturing Thereof
21 Dec 23
A semiconductor device and a method of manufacturing thereof are provided.
Min-Hsuan Lu, Kan-Ju Lin, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Chih-Hao Wang
Filed: 19 Jun 22
Utility
Method of Manufacturing a Semiconductor Device and a Semiconductor Device
21 Dec 23
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed.
Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
Filed: 25 May 22
Utility
Semiconductor Device and Manufacturing Method Thereof
21 Dec 23
A semiconductor device includes a channel region, first and second S/D contacts, first and second S/D epitaxial regions, a gate structure, and a gate contact.
Cheng-Ting Chung, Yu-Xuan Huang, Hou-Yu Chen, Jin Cai
Filed: 16 Jun 22
Utility
Methods of Manufacturing Semiconductor Devices and Semiconductor Devices
21 Dec 23
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space.
Che-Lun CHANG, Kuan-Ting PAN, Wei-Yang LEE, Chia-Pin LIN
Filed: 16 Jun 22