28912 patents
Page 23 of 1446
Utility
Semiconductor Device and Manufacturing Method Thereof
28 Dec 23
Disclosed is a semiconductor device and semiconductor fabrication method.
Chia-Ling Chung, Chun-Chih Cheng, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
Filed: 12 Jan 23
Utility
Semiconductor Device and Methods of Manufacturing
28 Dec 23
Some implementations described herein provide techniques and apparatuses for a stacked-die structure including a first integrated circuit device over a second integrated circuit device, where an operating voltage of the first integrated circuit device is different relative to an operating voltage of the second integrated circuit device.
Yu-Lun LU, Tsung-Chieh TSAI, Kong-Beng THEI, Yu-Chang JONG
Filed: 28 Jun 22
Utility
Device with Modified Work Function Layer and Method of Forming the Same
28 Dec 23
A semiconductor device includes a plurality of fin structures disposed over a substrate and a work function alloy layer disposed over each fin structure of the plurality of fin structures.
Yu-Chi PAN, Kuan-Wei Lin, Chun-Neng Lin, Yu-Shih Wang, Ming-Hsi Yeh, Kuo-Bin Huang
Filed: 24 Jun 22
Utility
Semiconductor Device and Method
28 Dec 23
Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact.
Kai-Qiang Wen, Shih-Fen Huang, Shih-Chun Fu, Chi-Yuan Shih, Feng Yuan, Wan-Lin Tsai, Chung-Liang Cheng
Filed: 24 Jun 22
Utility
Metal Layer Protection During Wet Etching
28 Dec 23
Disclosed is a method of fabricating a contact in a semiconductor device.
Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
Filed: 27 Jun 22
Utility
Semiconductor Device and Method of Manufacturing the Same
28 Dec 23
The present disclosure relates to semiconductor device with a multi-gate structure.
Chih-Kuan Yu, Shen-Hui Hong, Feng-Chi Hung, Wen-I Hsu, Jen-Cheng Liu, Dun-Nian Yaung
Filed: 23 Jun 22
Utility
Semiconductor Device and Manufacturing Method Thereof
28 Dec 23
Disclosed is a semiconductor device and semiconductor fabrication method.
Chia-Ling Chung, Chun-Chih Cheng, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
Filed: 27 Jun 22
Utility
Deep Trench Isolation Structure and Methods for Fabrication Thereof
28 Dec 23
A Deep Trench Isolation (DTI) structure is disclosed.
Kai-Yun YANG, Yu-Jen WANG
Filed: 27 Jun 22
Utility
Method for Forming Dual Silicide In Manufacturing Process of Semiconductor Structure
28 Dec 23
A method for manufacturing a semiconductor structure includes: forming a patterned structure which includes a first semiconductor portion and a second semiconductor portion, the first and second semiconductor portions having different materials; and performing an oxide formation process to oxidize the first and second semiconductor portions such that a first oxidation layer formed on the first semiconductor portion has a thickness less than that of a second oxidation layer formed on the second semiconductor portion.
Ying-Chi SU, Li-Wei CHU, Hung-Hsu CHEN, Chih-Wei CHANG, Ming-Hsing TSAI
Filed: 23 Jun 22
Utility
Mim Capacitor and Method of Forming the Same
28 Dec 23
A metal-insulator-metal (MIM) capacitor and methods of forming the same are described.
Hsing-Lien LIN, Hai-Dang TRINH, Yao-Wen CHANG, Jui-Lin CHU, Cheng-Te LEE
Filed: 27 Jun 22
Utility
Voltage Amplifier Based on Cascaded Charge Pump Boosting
28 Dec 23
Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting.
Chin-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
Filed: 10 Aug 23
Utility
High-voltage Semiconductor Devices and Methods of Formation
28 Dec 23
A high-voltage transistor may include a planar active region for a first source/drain active region, a second source/drain active region, and/or a channel active region.
Wan-Jyun SYUE, Hsueh-Liang CHOU, Yi-Jen LO
Filed: 27 Jun 22
Utility
Sense Amplifier Circuit, Memory Circuit, and Sensing Method Thereof
28 Dec 23
The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch.
Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
Filed: 22 Jun 22
Utility
Integrated Circuit with Bottom Dielectric Insulators and Fin Sidewall Spacers for Reducing Source/drain Leakage Currents
28 Dec 23
An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures.
Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
Filed: 27 Jun 22
Utility
Transistor Source/Drain Regions and Methods of Forming the Same
28 Dec 23
In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.
Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
Filed: 5 Jan 23
Utility
Semiconductor Device and Method of Manufacturing Thereof
28 Dec 23
A semiconductor device includes a field effect transistor disposed over a first main surface of a semiconductor substrate, a distributed Bragg reflector disposed over an opposing second main surface of the semiconductor substrate, and a conductive via disposed in the distributed Bragg reflector.
Wen-Yen CHEN, Tsai-Yu HUANG, Yee-Chia YEO
Filed: 24 Jun 22
Utility
Semiconductor Device with Reverse-cut Source/drain Contact Structure and Method Thereof
28 Dec 23
A method includes providing a structure having gate structures, source/drain electrodes, a first etch stop layer (ESL), a first interlayer dielectric (ILD) layer, a second ESL, and a second ILD layer.
Meng-Huan Jao, Lin-Yu Huang, Huan-Chieh Su
Filed: 22 Aug 22
Utility
Method for Forming Multi-gate Semiconductor Structure
28 Dec 23
A method for forming a multi-gate semiconductor structure is provided.
CHUN-MING YANG, YU-JIUN PENG, YU-WEN WANG
Filed: 26 Jun 22
Utility
Flip-flop with Transistors Having Different Threshold Voltages, Semiconductor Device Including Same and Methods of Manufacturing Same
28 Dec 23
A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters).
Xing Chao YIN, Huaixin XIAN, Hui-Zhong ZHUANG, Yung-Chen CHIEN, Jerry Chang Jui KAO, Xiangdong CHEN
Filed: 6 Jul 22
Utility
Pipelined Hybrid Noise-Shaping Analog-To-Digital Converter
28 Dec 23
Systems and methods are provided for implementing an analog-to-digital converter.
Martin Kinyua
Filed: 23 Jun 22