28912 patents
Page 20 of 1446
Utility
Packages with metal line crack prevention design
2 Jan 24
A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines.
Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
Filed: 29 Jun 21
Utility
Integrated circuit device
2 Jan 24
An integrated circuit (IC) device includes at least one delay circuit having an input and an output, and an output connector electrically coupled to the output.
Huaixin Xian, Yang Zhou, Qingchao Meng
Filed: 3 Jun 21
Utility
Tie off device
2 Jan 24
An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction.
Shao-Lun Chien, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue
Filed: 20 May 20
Utility
Trench isolation structure for image sensors
2 Jan 24
Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer.
Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chin-Chia Kuo, Wen-Hau Wu, Hua-Mao Chen, Chih-Kung Chang
Filed: 15 Jan 21
Utility
Semiconductor structure including MIM capacitor and method of forming the same
2 Jan 24
A method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers.
I-Che Lee
Filed: 16 Jul 21
Utility
Ultra-thin fin structure and method of fabricating the same
2 Jan 24
The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics.
Sherry Li, Chia-Der Chang, Yi-Jing Lee
Filed: 29 Nov 21
Utility
Semiconductor device and method
2 Jan 24
Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed.
Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
Filed: 6 Apr 21
Utility
Semiconductor device structure including forksheet transistors and methods of forming the same
2 Jan 24
A semiconductor device structure, along with methods of forming such, are described.
Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Chun-Fu Lu, Chih-Hao Wang, Kuan-Lun Cheng
Filed: 19 Mar 21
Utility
Conformal transfer doping method for fin-like field effect transistor
2 Jan 24
Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein.
Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
Filed: 28 Jul 22
Utility
Transistor, integrated circuit, and manufacturing method of transistor
2 Jan 24
A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode.
Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Tsuching Yang, Feng-Cheng Yang, Chung-Te Lin
Filed: 13 Aug 21
Utility
Input buffer circuit
2 Jan 24
An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit.
Yu-Kai Tsai, Chia-Hui Chen, Chia-Jung Chang
Filed: 3 Jun 21
Utility
Memory device and method thereof
2 Jan 24
A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value.
Jau-Yi Wu, Win-San Khwa, Jin Cai, Yu-Sheng Chen
Filed: 28 Jul 22
Utility
Ion implantation method and device
2 Jan 24
An ion implantation system comprising: a sample platform; an ion gun; an electrostatic linear accelerator; a direct current (DC) final energy magnet (FEM); and a processor.
Yi-Hsiung Lin, Yao-Jen Yeh, Chia-Lin Ou, Cheng-En Lee, Hsuan-Pang Liu
Filed: 1 Nov 21
Utility
Package structure and method of manufacturing the same
2 Jan 24
A method of forming a package structure includes the following steps.
Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
Filed: 31 Mar 22
Utility
Multi-wafer capping layer for metal arcing protection
2 Jan 24
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure.
Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
Filed: 4 Aug 22
Utility
Integrated circuit device with epitaxial features having adjusted profile and method for manufacturing the same
2 Jan 24
A method for manufacturing an integrated circuit device is provided.
Wen-Hsien Tu, Dong-Jie Ke
Filed: 30 Aug 21
Utility
Apparatus for detecting end point
2 Jan 24
An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller.
Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
Filed: 28 Mar 21
Utility
Semiconductor packages having conductive patterns of redistribution structure having ellipse-like shape
2 Jan 24
A semiconductor package includes a die, a redistribution structure and a plurality of conductive terminals.
Chia-Kuei Hsu, Ming-Chih Yew, Po-Chen Lai, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
Filed: 27 Aug 21
Utility
Semiconductor structures and methods of forming the same
2 Jan 24
A semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, a second dielectric feature, and a via contact.
Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
Filed: 3 Jun 21
Utility
Package structure and method of fabricating the same
2 Jan 24
Provided is a package structure, including a die, a plurality of through vias, an encapsulant, a plurality of first connectors, a warpage control material and a protection material.
Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
Filed: 24 Dec 21