28912 patents
Page 18 of 1446
Utility
Sidewall spacer to reduce bond pad necking and/or redistribution layer necking
2 Jan 24
In some embodiments, an integrated chip (IC) is provided.
Alexander Kalnitsky, Kong-Beng Thei
Filed: 21 Jul 22
Utility
3D trench capacitor for integrated passive devices
2 Jan 24
Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same.
Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
Filed: 20 Dec 21
Utility
Semiconductor device including source/drain contact having height below gate stack
2 Jan 24
A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.
Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun-Li Chen, Kam-Tou Sio, Shih-Wei Peng, Chun-Kuang Chen, Ru-Gun Liu
Filed: 10 Feb 23
Utility
Work function design to increase density of nanosheet devices
2 Jan 24
In some embodiments, the present disclosure relates to an integrated chip.
Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
Filed: 21 Feb 22
Utility
Nanostructure with various widths
2 Jan 24
A semiconductor structures and a method for forming the same are provided.
Hsiao-Han Liu, Chih-Hao Wang, Kuo-Cheng Chiang, Shi-Ning Ju, Kuan-Lun Cheng
Filed: 10 Jun 22
Utility
Wave guide filter for semiconductor imaging devices
2 Jan 24
In some embodiments, an image sensor is provided.
Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
Filed: 19 Jan 22
Utility
Gate structures for semiconductor devices
2 Jan 24
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed.
Chung-Liang Cheng, Chun-I Wu, Huang-Lin Chao
Filed: 28 Jun 21
Utility
Method of manufacturing a semiconductor device
2 Jan 24
In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.
Ming-Wen Hsiao, Chun-Yen Tai, Yen-Hsin Liu, Ming-Jhih Kuo, Ming-Feng Shieh
Filed: 23 Apr 21
Utility
Stacked multi-gate structure and methods of fabricating the same
2 Jan 24
A semiconductor device according to the present disclosure includes a stack of first channel layers and first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively.
Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng
Filed: 27 May 21
Utility
Semiconductor device and manufacturing method thereof
2 Jan 24
In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate.
Jiun Shiung Wu, Guan-Jie Shen
Filed: 9 Aug 21
Utility
Method for forming semiconductor device structure with nanowires
2 Jan 24
Structures and formation methods of a semiconductor device structure are provided.
Wilman Tsai, Cheng-Hsien Wu, I-Sheng Chen, Stefan Rusu
Filed: 30 Aug 21
Utility
Self-aligned spacers for multi-gate devices and method of fabrication thereof
2 Jan 24
A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature.
Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
Filed: 11 Apr 22
Utility
System and method of verifying slanted layout components
2 Jan 24
Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component.
Yuan-Te Hou, Min-Yuan Tsai
Filed: 6 Aug 21
Utility
Read circuit for magnetic tunnel junction (MTJ) memory
2 Jan 24
In some embodiments, the present application provides a memory device.
Gaurav Gupta, Zhiqiang Wu
Filed: 19 May 22
Utility
Buffer control of multiple memory banks
2 Jan 24
Disclosed herein are related to operating a memory system including memory banks and buffers.
Shih-LIen Linus Lu
Filed: 28 Jul 22
Utility
Fine line patterning methods
2 Jan 24
A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
Filed: 31 Jan 22
Utility
Semiconductor substrate bonding tool and methods of operation
2 Jan 24
A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks.
Yen-Hao Huang, Chun-Yi Chen, I-Shi Wang, Yin-Tun Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
Filed: 26 May 21
Utility
Semiconductor package and method of fabricating semiconductor package
2 Jan 24
A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate.
Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
Filed: 26 Feb 21
Utility
Through-substrate-via with reentrant profile
2 Jan 24
The present disclosure relates an integrated chip.
Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
Filed: 17 Feb 21
Utility
Integrated circuit conductive line arrangement for circuit structures, and method
2 Jan 24
A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type.
Chih-Yu Lai, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
Filed: 27 Aug 21