28912 patents
Page 18 of 1446
Utility
Memory cell and method of operating the same
2 Jan 24
A memory cell includes a write bit line, a read word line, a write transistor, and a read transistor.
Bo-Feng Young, Sai-Hooi Yeong, Chao-I Wu, Chih-Yu Chang, Yu-Ming Lin
Filed: 19 Jan 23
Utility
Memory device and operating method thereof
2 Jan 24
A memory device includes a first transistor, a second transistor and a third transistor.
He-Zhou Wan, Xiu-Li Yang, Mu-Yang Ye, Yan-Bo Song
Filed: 26 Oct 22
Utility
Memory device and method thereof
2 Jan 24
A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value.
Jau-Yi Wu, Win-San Khwa, Jin Cai, Yu-Sheng Chen
Filed: 28 Jul 22
Utility
Stressing algorithm for solving cell-to-cell variations in phase change memory
2 Jan 24
A process is provided to trim PCRAM cells to have consistent programming curves.
Jau-Yi Wu
Filed: 10 Aug 22
Utility
Memory circuit and method of operating same
2 Jan 24
A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell.
Chun-Hao Chang, Gu-Huan Li, Shao-Yu Chou
Filed: 18 Jan 23
Utility
Buffer control of multiple memory banks
2 Jan 24
Disclosed herein are related to operating a memory system including memory banks and buffers.
Shih-LIen Linus Lu
Filed: 28 Jul 22
Utility
MRAM stacks and memory devices
2 Jan 24
Memory stacks, memory devices and method of forming the same are provided.
Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
Filed: 29 Jul 22
Utility
Ion implantation method and device
2 Jan 24
An ion implantation system comprising: a sample platform; an ion gun; an electrostatic linear accelerator; a direct current (DC) final energy magnet (FEM); and a processor.
Yi-Hsiung Lin, Yao-Jen Yeh, Chia-Lin Ou, Cheng-En Lee, Hsuan-Pang Liu
Filed: 1 Nov 21
Utility
Fine line patterning methods
2 Jan 24
A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
Filed: 31 Jan 22
Utility
Semiconductor structure and method of manufacturing the same
2 Jan 24
A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantation cycles in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.
Chia-Chung Chen, Chung-Hao Chu, Chi-Feng Huang, Victor Chiang Liang
Filed: 14 Jun 22
Utility
Semiconductor device and method
2 Jan 24
In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.
Kuei-Lun Lin, Chia-Wei Hsu, Xiong-Fei Yu, Chi On Chui, Chih-Yu Hsu, Jian-Hao Chen
Filed: 29 Jan 21
Utility
Package structure and method of manufacturing the same
2 Jan 24
A method of forming a package structure includes the following steps.
Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
Filed: 31 Mar 22
Utility
Semiconductor substrate bonding tool and methods of operation
2 Jan 24
A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks.
Yen-Hao Huang, Chun-Yi Chen, I-Shi Wang, Yin-Tun Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
Filed: 26 May 21
Utility
FinFET device and method of forming same
2 Jan 24
A semiconductor device a method of forming the same are provided.
Bo-Cyuan Lu, Tai-Chun Huang, Chih-Tang Peng, Chi On Chui
Filed: 13 Jan 21
Utility
Semiconductor package and method of fabricating semiconductor package
2 Jan 24
A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate.
Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
Filed: 26 Feb 21
Utility
Multi-wafer capping layer for metal arcing protection
2 Jan 24
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure.
Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
Filed: 4 Aug 22
Utility
Integrated circuit device with epitaxial features having adjusted profile and method for manufacturing the same
2 Jan 24
A method for manufacturing an integrated circuit device is provided.
Wen-Hsien Tu, Dong-Jie Ke
Filed: 30 Aug 21
Utility
Apparatus for detecting end point
2 Jan 24
An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller.
Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
Filed: 28 Mar 21
Utility
Thermal substrate contact
2 Jan 24
An integrated circuit includes an oxide layer over a substrate; a layer of semiconductor material over the oxide layer and which includes a P-well, an N-well, and a channel of a transistor; and a thermal substrate contact extending through the layer of semiconductor material and the oxide layer, and against a top surface of the substrate.
Jian Wu, Feng Han, Shuai Zhang
Filed: 15 Dec 20
Utility
Method for forming semiconductor package
2 Jan 24
A method of forming a semiconductor package is provided.
Chin-Hua Wang, Po-Yao Lin, Feng-Cheng Hsu, Shin-Puu Jeng, Wen-Yi Lin, Shu-Shen Yeh
Filed: 14 May 21