28912 patents
Page 17 of 1446
Utility
Target control in extreme ultraviolet lithography systems using aberration of reflection image
2 Jan 24
A method of controlling an extreme ultraviolet (EUV) lithography system is disclosed.
Ting-Ya Cheng, Han-Lung Chang, Shi-Han Shann, Li-Jui Chen, Yen-Shuo Su
Filed: 23 May 22
Utility
Semiconductor manufacturing system, behavior recognition device and semiconductor manufacturing method
2 Jan 24
A behavior recognition device for recognizing behaviors of a semiconductor manufacturing apparatus includes a storage device and a control unit.
Kai-Ting Yang, Li-Jen Ko, Hsiang Yin Shen
Filed: 18 Aug 20
Utility
Circuit, semiconductor device and method for parameter PSRR measurement
2 Jan 24
A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator.
Amit Kundu, Jaw-Juinn Horng, Yi-Hsiang Wang
Filed: 16 Feb 22
Utility
Mask defect prevention
2 Jan 24
A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask.
Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
Filed: 30 Jun 22
Utility
Multi-metal fill with self-aligned patterning and dielectric with voids
2 Jan 24
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield.
Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
Filed: 19 Jul 22
Utility
Static random access memory cell
2 Jan 24
A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure.
Jordan Hsu, Yu-Kuan Lin, Shau-Wei Lu, Chang-Ta Yang, Ping-Wei Wang, Kuo-Hung Lo
Filed: 2 Jun 22
Utility
Semiconductor device including insulating element and method of making
2 Jan 24
A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate.
Chin-Shan Wang, Shun-Yi Lee
Filed: 8 Jul 21
Utility
Memory cell, method of forming the same, and semiconductor device having the same
2 Jan 24
Yu-Chao Lin, Tung-Ying Lee
Filed: 27 Apr 22
Utility
MRAM fabrication and device
2 Jan 24
A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
Filed: 30 Aug 21
Utility
Memory device and SRAM cell
2 Jan 24
A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor.
Hung-Yu Ye, Chung-Yi Lin, Yun-Ju Pan, Chee-Wee Liu
Filed: 10 Mar 22
Utility
Semiconductor device and method of manufacturing the same
2 Jan 24
In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area.
Meng-Han Lin, Chih-Ren Hsieh, Ching-Wen Chan
Filed: 3 Jan 22
Utility
Memory device, integrated circuit device and method
2 Jan 24
A memory device includes a bit line, a word line, a memory cell, select bit lines, and a controller.
Meng-Han Lin, Sai-Hooi Yeong, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin
Filed: 19 Jan 23
Utility
Magnetic random access memory and manufacturing method thereof
2 Jan 24
In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed.
Shy-Jay Lin, Chwen Yu, William J. Gallagher
Filed: 26 Jul 21
Utility
Integrated circuit fin structure manufacturing method
2 Jan 24
A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins.
Po-Hsiang Huang, Fong-Yuan Chang, Clement Hsingjen Wann, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien, Chia-Ming Hsu
Filed: 13 Dec 22
Utility
Stressing algorithm for solving cell-to-cell variations in phase change memory
2 Jan 24
A process is provided to trim PCRAM cells to have consistent programming curves.
Jau-Yi Wu
Filed: 10 Aug 22
Utility
MRAM stacks and memory devices
2 Jan 24
Memory stacks, memory devices and method of forming the same are provided.
Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
Filed: 29 Jul 22
Utility
FinFET device and method of forming same
2 Jan 24
A semiconductor device a method of forming the same are provided.
Bo-Cyuan Lu, Tai-Chun Huang, Chih-Tang Peng, Chi On Chui
Filed: 13 Jan 21
Utility
Method for forming semiconductor package
2 Jan 24
A method of forming a semiconductor package is provided.
Chin-Hua Wang, Po-Yao Lin, Feng-Cheng Hsu, Shin-Puu Jeng, Wen-Yi Lin, Shu-Shen Yeh
Filed: 14 May 21
Utility
Package structure and method of manufacturing the same
2 Jan 24
A package structure includes a semiconductor die and a first redistribution circuit structure.
Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
Filed: 29 Oct 21
Utility
Semiconductor devices with backside routing and method of forming same
2 Jan 24
In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
Filed: 18 Dec 20