28912 patents
Page 19 of 1446
Utility
Through-substrate-via with reentrant profile
2 Jan 24
The present disclosure relates an integrated chip.
Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
Filed: 17 Feb 21
Utility
Semiconductor packages having conductive patterns of redistribution structure having ellipse-like shape
2 Jan 24
A semiconductor package includes a die, a redistribution structure and a plurality of conductive terminals.
Chia-Kuei Hsu, Ming-Chih Yew, Po-Chen Lai, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
Filed: 27 Aug 21
Utility
Interposer and semiconductor package each having conductive terminals on redistribution layer with different pitch
2 Jan 24
An interposer, including a redistribution layer structure, first conductive terminals, and second conductive terminals, is provided.
Yu-Ju Chang, Jia-Liang Chen, Chun-Hong Chen
Filed: 18 Nov 21
Utility
Semiconductor structures and methods of forming the same
2 Jan 24
A semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, a second dielectric feature, and a via contact.
Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
Filed: 3 Jun 21
Utility
Package structure and method of manufacturing the same
2 Jan 24
A package structure includes a semiconductor die and a first redistribution circuit structure.
Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
Filed: 29 Oct 21
Utility
Semiconductor devices with backside routing and method of forming same
2 Jan 24
In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
Filed: 18 Dec 20
Utility
Integrated circuit conductive line arrangement for circuit structures, and method
2 Jan 24
A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type.
Chih-Yu Lai, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
Filed: 27 Aug 21
Utility
Package structure and method of fabricating the same
2 Jan 24
Provided is a package structure, including a die, a plurality of through vias, an encapsulant, a plurality of first connectors, a warpage control material and a protection material.
Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
Filed: 24 Dec 21
Utility
Semiconductor package
2 Jan 24
A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener.
Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
Filed: 27 Jul 22
Utility
Semiconductor device and method
2 Jan 24
In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.
Chen-Shien Chen, Ting-Li Yang, Po-Hao Tsai, Chien-Chen Li, Ming-Da Cheng
Filed: 18 May 21
Utility
Integrated circuit package and method of forming thereof
2 Jan 24
A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.
Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
Filed: 29 Jun 21
Utility
Sidewall spacer to reduce bond pad necking and/or redistribution layer necking
2 Jan 24
In some embodiments, an integrated chip (IC) is provided.
Alexander Kalnitsky, Kong-Beng Thei
Filed: 21 Jul 22
Utility
Package structure with solder resist underlayer for warpage control and method of manufacturing the same
2 Jan 24
A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer.
Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
Filed: 18 Dec 19
Utility
Bonding to alignment marks with dummy alignment marks
2 Jan 24
A method includes placing a first package component.
Hsien-Wei Chen, Ying-Ju Chen, Ming-Fa Chen
Filed: 20 May 21
Utility
Integrated circuit package and method of forming same
2 Jan 24
A package and a method of forming the same are provided.
Ming-Fa Chen, Hsien-Wei Chen, Chen-Hua Yu
Filed: 4 Jan 21
Utility
Packages with metal line crack prevention design
2 Jan 24
A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines.
Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
Filed: 29 Jun 21
Utility
3D trench capacitor for integrated passive devices
2 Jan 24
Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same.
Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
Filed: 20 Dec 21
Utility
Power gating cell structure
2 Jan 24
A power gating cell on an integrated circuit is provided.
Wei-Ling Chang, Jung-Chan Yang, Li-Chun Tien, Ting Yu Chen
Filed: 15 Sep 20
Utility
Integrated circuit device
2 Jan 24
An integrated circuit (IC) device includes at least one delay circuit having an input and an output, and an output connector electrically coupled to the output.
Huaixin Xian, Yang Zhou, Qingchao Meng
Filed: 3 Jun 21
Utility
Semiconductor device including source/drain contact having height below gate stack
2 Jan 24
A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.
Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun-Li Chen, Kam-Tou Sio, Shih-Wei Peng, Chun-Kuang Chen, Ru-Gun Liu
Filed: 10 Feb 23