28912 patents
Page 44 of 1446
Utility
Conductive Structures and Methods of Forming the Same
7 Dec 23
Depositing a seed layer after formation of the MD in order to reduce or prevent epitaxial growth of the seed layer toward the MD.
Kan-Ju LIN, Hao-Heng LIU, Chien CHANG, Hung-Yi HUANG, Harry CHIEN
Filed: 6 Jun 22
Utility
Integrated Circuit Device and Manufacturing Method of the Same
7 Dec 23
A method is provided, including following operations: obtaining information on gate pitch and a ratio between the gate pitch and a first metal line pitch; comparing a preset metal line end spacing with a second metal line pitch, of multiple metal traces, and a spacing between a metal line layer and a power rail layer; in response to the comparison, defining multiple first metal line patterns overlapping multiple first gate patterns and defining multiple second metal line patterns disposed between two adjacent gate patterns in multiple second gate patterns; placing the first metal line patterns in a first row in a floorplan of an integrated circuit layout design and the second metal line patterns in a second row, adjacent the first row; and manufacturing at least one element in an integrated circuit based on the integrated circuit layout design.
Shih-Wei PENG, Wei-Cheng TZENG, Wei-Cheng LIN, Jiann-Tyng TZENG
Filed: 1 Jun 22
Utility
Semiconductor Devices with Low Leakage Current and Methods of Fabricating the Same
7 Dec 23
Semiconductor devices and methods are provided.
Ming-Yuan Wu, Ka-Hing Fung, Min Jiao, Da-Wen Lin, Wei-Yuan Jheng
Filed: 7 Jun 22
Utility
Semiconductor Device and Manufacturing Method Thereof
7 Dec 23
A semiconductor device includes a substrate, an interconnect, a second transistor, and a sensing film.
Wei Lee, Chung-Liang Cheng, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
Filed: 2 Jun 22
Utility
Semiconductor Structures And Methods Of Forming The Same
7 Dec 23
Passive devices are provided.
Mao-Nan Wang, Yuan-Yang Hsiao, Chen-Chiu Huang, Dian-Hau Chen
Filed: 3 Jun 22
Utility
Detection Method of Euv Pellicle Status
7 Dec 23
A method includes transferring an inner pod of a carrier out from an outer pod of the carrier into a lithography exposure apparatus, the inner pod containing a reticle including a reflective multilayer and a pellicle underlying the reflective multilayer; detecting a condition of the pellicle using a metrology device positioned on a base plate of the inner pod during transferring the inner pod in the lithography exposure apparatus; determining whether the condition of the pellicle is acceptable; issuing a warning when the condition of the pellicle is not acceptable.
Yen-Hao LIU, Shao-Hua WANG, Zheng-Hao ZHANG, Fan-Chi LIN, Chueh-Chi KUO, Li-Jui CHEN, Heng-Hsin LIU
Filed: 1 Jun 22
Utility
Metal Pillars Preventing Wetting on Sidewalls and Method Forming Same
7 Dec 23
A package includes a first package component, which includes a bottom dielectric layer, a micro-bump protruding below the bottom dielectric layer, and a metal pillar protruding below the bottom dielectric layer.
Po-Chen Lai, Ming-Chih Yew, Li-Ling Liao, Shu-Shen Yeh, Shin-Puu Jeng
Filed: 2 Jun 22
Utility
Method of Making Integrated Circuit with Backside Interconnections
7 Dec 23
A method of making an integrated includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact.
Shih-Wei PENG, Te-Hsin CHIU, Wei-An LAI, Ching-Wei TSAI, Jiann-Tyng TZENG
Filed: 10 Aug 23
Utility
Semiconductor Package and Methods of Manufacturing
7 Dec 23
Some implementations described herein provide techniques and apparatuses for a semiconductor package.
Po-Chen LAI, Ming-Chih YEW, Shu-Shen YEH, Po-Yao LIN, Shin-Puu JENG
Filed: 2 Jun 22
Utility
Bond Pad Structure Coupled to Multiple Interconnect Conductive\ Structures Through Trench In Substrate
7 Dec 23
In some embodiments, the present disclosure relates to a device that includes an interconnect structure arranged on a frontside of a substrate.
Ming Chyi Liu
Filed: 8 Aug 23
Utility
Semiconductor Package and Method of Manufacturing Semiconductor Package
7 Dec 23
A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure.
Hsien-Wei Chen, Ming-Fa Chen
Filed: 8 Aug 23
Utility
Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices
7 Dec 23
Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed.
Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
Filed: 10 Aug 23
Utility
Image Sensor and Manufacturing Method Thereof
7 Dec 23
An image sensor includes a pixel and an isolation structure.
Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
Filed: 9 Aug 23
Utility
Seal Ring for Semiconductor Device
7 Dec 23
A method includes providing a structure having a substrate and first and second semiconductor layers alternately stacked one over another above the substrate, etching the first and the second semiconductor layers to form a first continuous ring in a seal ring region of the structure, and forming an isolation structure adjacent the first continuous ring in the seal ring region.
Chun Yu Chen, Yen Lian Lai
Filed: 5 Jun 22
Utility
Multi-gate Device and Method of Fabrication Thereof
7 Dec 23
A method includes forming a semiconductor fin protruding from a substrate, forming a cladding layer on sidewalls of the semiconductor fin, forming first and second dielectric fins sandwiching the semiconductor fin, and removing the cladding layer.
Ko-Cheng Liu, Chang-Miao Liu, Huiling Shang
Filed: 5 Jun 22
Utility
Semiconductor Structure and Method for Forming the Same
7 Dec 23
A method for forming a semiconductor structure is provided.
Tai-Yuan WANG
Filed: 6 Jun 22
Utility
Semiconductor Device with Gate Isolation Features and Fabrication Method of the Same
7 Dec 23
A semiconductor device includes a first channel member over a first backside dielectric feature, a first gate structure engaging the first channel member, a second channel member over a second backside dielectric feature, a second gate structure engaging the second channel member, and a first isolation feature includes a first portion laterally between the first and second backside dielectric features and a second portion laterally between the first and second gate structures.
Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Jia-Chuan You, Chia-Hao Chang, Chih-Hao Wang, Kuan-Lun Cheng
Filed: 10 Aug 23
Utility
Method of Manufacturing Semiconductor Devices and Semiconductor Devices
7 Dec 23
A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate.
Yu-Ming CHEN, Szu-Ying CHEN, Yen-Chun HUANG, Sen-Hong SYUE, Huicheng CHANG, Yee-Chia YEO
Filed: 3 Jun 22
Utility
Memory Computation Method
7 Dec 23
A method of performing an in-memory computation includes storing a first subset of data in a first segment of a first memory array and a second subset of the data in a second segment of the first memory array, latching a first data bit from a first column of memory cells in the first segment of the first memory array, sequentially reading a plurality of second data bits from a second column of memory cells in the second segment of the first memory array, and performing a logic operation on each combination of the latched first data bit and each second data bit.
Yen-Huei CHEN, Hidehiro FUJIWARA, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG
Filed: 10 Aug 23
Utility
Floating Data Line Circuit and Method
7 Dec 23
A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals.
Manish ARORA, Yen-Huei CHEN, Hung-Jen LIAO, Nikhil PURI, Yu-Hao HSU
Filed: 31 Jul 23