28912 patents
Page 67 of 1446
Utility
Silicon-germanium Fins and Methods of Processing the Same In Field-effect Transistors
30 Nov 23
A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
Filed: 9 Aug 23
Utility
Process and Structure for Source/drain Contacts
30 Nov 23
A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.
Meng-Huan Jao, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
Filed: 28 Jul 23
Utility
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30 Nov 23
Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein.
Chun-Hsien Huang, Chang-Ting Chung, Wei-Cheng Lin, Wei-Jung Lin, Chih-Wei Chang
Filed: 9 Aug 23
Utility
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30 Nov 23
A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material.
Po-Chuan Wang, Chia-Yang Hung, Sheng-Liang Pan
Filed: 9 Aug 23
Utility
d92t7bie518inhxzayubtke4q8k8k2248xg3bzg3v4ddj1pl8qbuttkp 1ed
30 Nov 23
A semiconductor structure and a method of forming the same are provided.
Po-Yu Huang, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
Filed: 27 Jul 23
Utility
fup4c3sie1252bdysz9f6n90ozbdqflxv0xvi 7fnwbif2q3behzjg
30 Nov 23
A first interconnect structure (e.g., a gate interconnect) of a butted contact (BCT) is etched and filled.
Te-Chih HSIUNG, I-Hung LI, Yi-Ruei JHAN, Yuan-Tien TU
Filed: 10 Aug 23
Utility
4x1sy4ig40r873n1s5ngh9cpq2mrw
30 Nov 23
A semiconductor device a method of forming the same are provided.
Pei-Yu Chou, Jr-Hung Li, Tze-Liang Lee
Filed: 7 Aug 23
Utility
xs7vfb6ik3k40rjm2ot7eigy10qlx59ltvorifxgrf12elpzl4pj7wn35xc
30 Nov 23
A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component.
Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
Filed: 9 Aug 23
Utility
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30 Nov 23
A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups.
Tze-Liang Lee
Filed: 7 Aug 23
Utility
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30 Nov 23
In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.
Yung-Hsiang CHAN, An-Hung TAI, Hui-Chi CHEN, J.F. CHUEH, Yen-Ta LIN, Ming-Chi HUANG, Cheng-Chieh TU, Jian-Hao CHEN, Kuo-Feng YU
Filed: 24 May 22
Utility
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30 Nov 23
A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer.
Chao-Ching Cheng, Yi-Tse Hung, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li, Jin Cai
Filed: 6 Aug 23
Utility
ko59jfbbffn9zjfnmb5im0qpxm0k5kzv k14m8bvhzcze
30 Nov 23
Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature.
Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Chih-Hao WANG, Kuan-Lun CHENG
Filed: 8 Aug 23
Utility
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30 Nov 23
Source/drain silicide that improves performance and methods for fabricating such are disclosed herein.
Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Chung-Wei Wu, Zhiqiang Wu
Filed: 9 Aug 23
Utility
yvmzlh2lppmavtzs5onza6xdjotmtuv8af8rz
30 Nov 23
A semiconductor device includes a substrate having a P-well region, an N-well region disposed on either side of and abutting the P-well region, and a deep N-well region disposed beneath and abutting both the P-well region and at least part of the N-well region on either side of the P-well region.
Wen-Shun LO, Yu-Chi CHANG, Yingkit Felix TSUI
Filed: 26 May 22
Utility
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30 Nov 23
A semiconductor device includes a substrate, a first source/drain feature and a second source/drain feature over the substrate, a first semiconductor layer and a second semiconductor layer between the first and the second source/drain features, and a gate between the first and the second source/drain features.
Shih-Cheng Chen, Kuo-Cheng Chiang, Zhi-Chang Lin
Filed: 9 Aug 23
Utility
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30 Nov 23
A semiconductor structure is provided.
Anhao CHENG, Yen-Yu CHEN, Fang-Ting Kuo
Filed: 10 Aug 23
Utility
bjya3aihev9mf1k61n8s9t7z2z3o 1u6i3yre8xpdtecmt
30 Nov 23
A device includes a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate region over the semiconductor layer, wherein the second gate region has a second gate length equal to the first gate length; and a second spacer on a sidewall of second gate region, wherein the second spacer is wider than the first spacer.
Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang
Filed: 9 Aug 23
Utility
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30 Nov 23
A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap.
Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen
Filed: 8 Aug 23
Utility
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30 Nov 23
A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin.
Chi-Wen LIU, Chao-Hsiung WANG
Filed: 7 Aug 23
Utility
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30 Nov 23
Methods for making transistors with a semiconducting monolayer and low contact resistance are disclosed.
Po-Hsun Ho
Filed: 27 May 22