28912 patents
Page 64 of 1446
Utility
Semiconductor Package Crosstalk Reduction
30 Nov 23
A semiconductor package according to the present disclosure includes a routing structure, a first die and a second die disposed over the routing structure, a first array of contact features disposed along a first direction and electrically coupling the first die to the routing structure, and a second array of contact features disposed along the first direction and electrically coupling the second die to the routing structure.
Shu-Chun Yang, Wei Chih Chen
Filed: 25 May 22
Utility
Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via
30 Nov 23
The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines.
Kam-Tou SIO, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
Filed: 10 Aug 23
Utility
96wap1sev15h92y n2tigadjmk6sspa58iykbetjquhsvh7m6lznx
30 Nov 23
A semiconductor device includes an interposer disposed on a substrate.
Cheng-Chieh HSIEH, Hau TAO, Yung-Tien KUO
Filed: 7 Aug 23
Utility
qu6kx5ncv1o1qd2e 67bg6td21
30 Nov 23
A semiconductor package includes a first package component comprising: an integrated circuit die; an encapsulant surrounding the integrated circuit die; and a fan-out structure electrically connected to the integrated circuit die, wherein a first opening extends completely through the fan-out structure and at least partially through the encapsulant in a cross-sectional view, and wherein the encapsulant at least completely surrounds the first opening in a top-down view.
Sung-Yueh Wu, Jen-Chun Liao, Mao-Yen Chang, Yu-Chia Lai, Chien Ling Hwang, Ching-Hua Hsieh
Filed: 4 Aug 22
Utility
9zhsn3xnhf tdwo2vpjt
30 Nov 23
A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.
Feng-Wei Kuo, Wen-Shiang Liao
Filed: 7 Aug 23
Utility
2ctb4mndgtcmukadge087ufzboomsefq333uq8chq
30 Nov 23
A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer.
Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
Filed: 8 Aug 23
Utility
7zislvnxw6dbsnacblow487xd
30 Nov 23
In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.
Wen-Chih Chiou, Chen-Hua Yu, Shih Ting Lin, Szu-Wei Lu
Filed: 4 Aug 23
Utility
ldmctiss6vj4a6c5o9zcip s27bcbo3
30 Nov 23
In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.
Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
Filed: 9 Aug 23
Utility
i9xyjwscyo453jdj2rpbp2zcy34pj2sa4prl0jjh cah01ypvli5299c12yj
30 Nov 23
A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate.
Yu-Sheng Lin, Shu-Shen Yeh, Ming-Chih Yew, Chin-Hua Wang, Shin-Puu Jeng
Filed: 24 May 22
Utility
hvby109g5t41uyskc2clsm3e llxcjkl8985dlm5rm2a1h
30 Nov 23
A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.
Kai-Tai Chang, Tung Ying Lee
Filed: 26 Jul 23
Utility
hlt9yqclz3m4k8x1jtvf7g44kqi2485nd01g6 6icnilc746y1nkb5lo
30 Nov 23
Some implementations described herein provide a semiconductor structure.
Chung-Liang CHENG
Filed: 31 Jul 23
Utility
fc0o6rg5pl0866g x0brvgftv2ds0kz6glv4r
30 Nov 23
A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding.
Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
Filed: 31 Jul 23
Utility
nov8d5q4axvyo95ctxzaiy0hbmzliyloc6nucjn
30 Nov 23
A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.
Chang-Yi Yang, Po-Yao Chuang, Shin-Puu Jeng
Filed: 8 Aug 23
Utility
wjlqcgcemeftyozchdac2ljsdqb7hjqspc0ctufqu3j 0qb5695bs
30 Nov 23
In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.
Pei-Haw Tsao, Chien-Li Kuo, Kuo-Chio Liu
Filed: 31 May 22
Utility
5t3hfdjmepwvzmd67v49sv5b5 vwjtquujhbr7
30 Nov 23
A method (of manufacturing a semiconductor device) includes generating a corresponding layout diagram including: regarding first and second active area patterns which (1) are correspondingly nearest to a boundary between, and (2) are correspondingly in, first and second abutting cells, and for each gate pattern that intersects the first or second active area pattern, selecting the gate patterns for which a first distance from a nearest corresponding via-to-gate (VG) pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each selected gate pattern, relative to a first size, setting a size of a corresponding cut-gate section to a second size; the first size otherwise resulting in an overhang of a gate remnant portion extending towards the boundary by a first length; and the second size resulting in the overhang extending by a second length smaller than the first length.
Te-Hsin CHIU, Shih-Wei PENG, Jiann-Tyng TZENG
Filed: 10 Aug 23
Utility
4hozxdsz3i1yysk0 14gh73
30 Nov 23
A semiconductor device and a method of forming the same are provided.
Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin
Filed: 26 Jul 23
Utility
m08b9j7o1owo8nx0n2lt9ro58bxmvz3v2hsc9z2a9xefr0sivh
30 Nov 23
A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate.
YUAN-CHENG YANG, YUN-CHI WU, TSU-HSIU PERNG, SHIH-JUNG TU, CHENG-BO SHU, CHIA-CHEN CHANG
Filed: 26 May 22
Utility
49l73tdezy4xd1jgytkf31 j9b18lpwwzucrols5ka6aqmd1yl75y3mtn12
30 Nov 23
An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate.
Kuo-Cheng CHIANG, Jung-Chien CHENG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
Filed: 10 Aug 23
Utility
xokuqdla2idkieeihy6psfpbc ba5fl3cyz5uj7gg
30 Nov 23
A semiconductor structure includes a substrate, a first FET device and a second FET device.
JHU-MIN SONG, CHIEN-CHIH CHOU, YU-CHANG JONG
Filed: 26 May 22
Utility
p41kw65w015k84nh875x3f9nntz2qgigwpigmrcnlqkf9g2o9zoi3otmpk
30 Nov 23
A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.
Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
Filed: 26 Jul 23