28912 patents
Page 62 of 1446
Utility
Metal Gate Process and Related Structure
30 Nov 23
A method of forming a semiconductor device includes providing a device having a gate stack with a metal gate layer and a spacer layer disposed on a sidewall of the gate stack.
Chih-Lun LU, Jih-Sheng YANG, Chen-Wei PAN, Chih-Teng LIAO
Filed: 26 May 22
Utility
Semiconductor Device and Method of Manufacture
30 Nov 23
A semiconductor device such as a fin field effect transistor and its method of manufacture are provided.
Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang
Filed: 9 Aug 23
Utility
fkxaa6ipt5d1lx3c4dq8kpfurn
30 Nov 23
A method includes forming a first fin-group having has a plurality of semiconductor fins, and a second fin-group.
Shahaji B. More
Filed: 28 Jul 23
Utility
y6mfg9edu6vacq7k2i963 vfy2y9psxirjk8rdm4qma7h440g
30 Nov 23
A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers.
Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
Filed: 2 Aug 23
Utility
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30 Nov 23
The present disclosure describes fabricating devices with tunable gate height and effective capacitance.
Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
Filed: 4 Aug 23
Utility
0gu5cxoqci5wd50coil2jt pgcs8qw
30 Nov 23
A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.
Chieh-Ping Wang, Ting-Gang Chen, Bo-Cyuan Lu, Tai-Chun Huang, Chi On Chui
Filed: 1 Aug 23
Utility
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30 Nov 23
A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein.
Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
Filed: 7 Aug 23
Utility
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30 Nov 23
Disclosed is a method of forming a semiconductor device.
Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
Filed: 26 Jul 23
Utility
1jzcjjfyad5mhq3j8d2d5k6r6
30 Nov 23
A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer.
Huiching Chang, I-Ming Chang, Huang-Lin Chao
Filed: 9 Aug 23
Utility
9mzzbuym3euou n4ufiw029q7qbuhp3czbnd2dnvj5j60xam6dt7
30 Nov 23
Costs may be avoided and yields improved by applying scanning probe microscopy to substrates in the midst of an integrated circuit fabrication process sequence.
I-Che Lee, Huai-Ying Huang
Filed: 26 Jul 23
Utility
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30 Nov 23
A deposition system is provided capable of measuring at least one of the film characteristics (e.g., thickness, resistance, and composition) in the deposition system.
Wen-Hao CHENG, Yen-Yu CHEN, Yi-Ming DAI
Filed: 28 Jul 23
Utility
b1nh3c7hxoc4bx4hl8chl3p6gfj0p1v35i
30 Nov 23
A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material.
Yin-Jie Pan, Yu-Yun Peng
Filed: 9 Aug 23
Utility
pmq0zdy360ju5wmxogk z9nq092nb3l6gb3r3g2s8enif
30 Nov 23
A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall.
You-Ru Lin, Sheng Kai Yeh, Jen-Yuan Chang, Chi-Yuan Shih, Chia-Ming Hung, Hsiang-Fu Chen, Shih-Fen Huang
Filed: 25 May 22
Utility
ax10qptn5bce48h1dstrfgpw2gij8ud0wfm1rn
30 Nov 23
In an embodiment, a package including: a redistribution structure including a first dielectric layer and a first conductive element disposed in the first dielectric layer; a first semiconductor device bonded to the redistribution structure, wherein the first semiconductor device includes a first corner; and an underfill disposed over the redistribution structure and including a first protrusion extending into the first dielectric layer of the redistribution structure, wherein the first protrusion of the underfill overlaps the first corner of the first semiconductor device in a plan view.
Yu-Sheng Lin, Chien-Tung Yu, Chia-Hsiang Lin, Chin-Hua Wang, Shin-Puu Jeng
Filed: 31 May 22
Utility
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30 Nov 23
A package and a method forming the same are provided.
Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
Filed: 10 Aug 23
Utility
al9v61bv9ya6llmvszwz4y9
30 Nov 23
A stacked semiconductor device includes a cooling structure to increase the cooling efficiency of the stacked semiconductor device.
Jen-Yuan CHANG
Filed: 8 Aug 23
Utility
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30 Nov 23
An integrated circuit includes a substrate and a semiconductor material layer over the substrate.
Jian WU, Feng HAN, Shuai ZHANG
Filed: 10 Aug 23
Utility
sdosmthau6qtjtgv4wzoa3q vzjbpgcsv9zojbiptmyilcg06hd
30 Nov 23
In a method of forming a heat dissipating structure for a semiconductor chip, a soldering material is disposed on a top surface of the semiconductor chip.
Chang-Jung HSUEH, Yen Wei CHANG, Cheng-Nan LIN, Wei-Hung LIN, Ming-Da CHENG
Filed: 31 May 22
Utility
blf7y7ntrt1r9nj5ufbwizstawq kzry0my2sp60jdfmnq0vb906l
30 Nov 23
Methods of forming through vias for providing connections between a front-side of a substrate and a backside of the substrate and semiconductor devices including the same are disclosed.
Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Chih-Hao Wang
Filed: 4 Jan 23
Utility
dta0br6mkn602qa5yohdfonf9novdejslirtjerav86hu4g
30 Nov 23
Package structures and methods of forming package structures are described.
Chen-Hua Yu, Chih-Hua Chen, Hao-Yi Tsai, Yu-Feng Chen
Filed: 8 Aug 23