28912 patents
Page 65 of 1446
Utility
Fin End Isolation Structure for Semiconductor Devices
30 Nov 23
A method includes forming a fin protruding from a substrate, forming first and second gate structures across the fin, the first gate structure having a first gate sidewall facing the second gate structure, the second gate structure having a second gate sidewall facing the first gate structure, recessing a segment of the fin between the first and second gate sidewalls to form a trench, depositing a dielectric layer over the first and second gate sidewalls and within the trench, and depositing an inter-layer dielectric layer over the first and second gate structures and over the dielectric layer.
JHON JHY Liaw
Filed: 27 Jul 23
Utility
Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same
30 Nov 23
A semiconductor device includes a substrate having a first region and a second region.
Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
Filed: 27 Jul 23
Utility
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30 Nov 23
A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
Filed: 28 Jul 23
Utility
gy1 8dic8zwrfm991pobdlbzs5ey8ec8l232puogtk8j0d9wef
30 Nov 23
A semiconductor device structure, along with methods of forming such, are described.
Jui-Chien HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG, Shi Ning JU, Guan-Lin CHEN
Filed: 3 Aug 23
Utility
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30 Nov 23
Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein.
Jhon Jhy Liaw
Filed: 27 Jul 23
Utility
yghtya5vbfwb86u3xqwab7rwisso6mlf7zlv5erprvwn2t7poq7vm
30 Nov 23
A semiconductor structure includes: a substrate and a fin protruding from the substrate.
WEI-LUN CHEN
Filed: 28 Jul 23
Utility
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30 Nov 23
A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack.
Kuan-Ting Pan, Chih-Hao Wang, Shi Ning Ju, Jia-Chuan You, Kuo-Cheng Chiang
Filed: 28 Jul 23
Utility
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30 Nov 23
An embodiment device includes: an isolation region on a substrate; a first fin extending above a top surface of the isolation region; a gate structure on the first fin; and an epitaxial source/drain region adjacent the gate structure, the epitaxial source/drain region having a first main portion and a first projecting portion, the first main portion disposed in the first fin, the first projecting portion disposed on a first sidewall of the first fin and beneath the top surface of the isolation region.
Shahaji B. More
Filed: 4 Aug 23
Utility
q129fcavjm4swenj9u024e3pyfkccrezzs9
30 Nov 23
The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.
Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
Filed: 7 Aug 23
Utility
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30 Nov 23
An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via.
Chin-Wei HSU, Shun Li CHEN, Ting Yu CHEN, Hui-Zhong ZHUANG, Chih-Liang CHEN
Filed: 31 May 22
Utility
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30 Nov 23
Various embodiments of the present disclosure are directed towards an integrated chip (IC).
Harry-Hak-Lay Chuang, Hsin Fu Lin, Chien Hung Liu
Filed: 8 Aug 23
Utility
54ewl4jafc0g6o85n4y3dhzvq1jhbii560ljbx6b352ix ns45vaklu2c
30 Nov 23
Various embodiments of the present disclosure are directed towards an image sensor.
Ming Chyi Liu, Jiech-Fun Lu
Filed: 27 Jul 23
Utility
9whhpp2m242mn5z0uq4e2kgh82xbvsfj0il69bpnhuwlh5xfn9nnf2op
30 Nov 23
An image sensor with high quantum efficiency is provided.
Chien-Chang Huang, Chien Nan Tu, Ming-Chi Wu, Yu-Lung Yeh, Ji Heng Jiang
Filed: 3 Aug 23
Utility
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30 Nov 23
A pixel sensor includes a transfer fin field effect transistor (finFET) to transfer a photocurrent from a photodiode to a drain region.
Feng-Chien HSIEH, Yun-Wei CHENG, Wei-Li HU, Kuo-Cheng LEE, Cheng-Ming WU
Filed: 10 Aug 23
Utility
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30 Nov 23
A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers.
Wei-Lin CHEN, Ching-Chung SU, Chun-Hao CHOU, Kuo-Cheng LEE
Filed: 9 Aug 23
Utility
mpbakbvfb8g7hyrqzjc2vqqiccpiaofshm62jnuna8rcjf ay9j873i1f
30 Nov 23
In some embodiments, an image sensor is provided.
Shih-Hsun Hsu, Ping-Hao Lin
Filed: 3 Aug 23
Utility
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30 Nov 23
Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction.
Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
Filed: 9 Aug 23
Utility
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30 Nov 23
Various embodiments of the present disclosure are directed towards an integrated chip including an optical device within or on a semiconductor substrate.
Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou, Tzu-Ming Wang
Filed: 28 Jul 23
Utility
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30 Nov 23
The present disclosure relates to an integrated chip including a semiconductor layer and a photodetector disposed along the semiconductor layer.
Yi-Hsien Chang, Shih-Fen Huang, Chun-Ren Cheng, Fu-Chun Huang, Ching-Hui Lin
Filed: 25 May 22
Utility
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30 Nov 23
The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation.
Cheng-Ta Wu, Kuo-Hwa Tzeng, Yeur-Luen Tu
Filed: 3 Aug 23