28912 patents
Page 68 of 1446
Utility
Self-aligned Inner Spacer on Gate-all-around Structure and Methods of Forming the Same
30 Nov 23
Semiconductor device and the manufacturing method thereof are disclosed herein.
Tsungyu Hung, Pang-Yen Tsai, Pei-Wei Lee
Filed: 26 Jul 23
Utility
Semiconductor Structure and Method for Manufacturing Thereof
30 Nov 23
A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact.
Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
Filed: 9 Aug 23
Utility
czqc3zgkv8ybkxxb4wj5cks5aia5e9r54s20u
30 Nov 23
Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein.
Sheng-Chou Lai, Tsung-Yu Chiang
Filed: 10 Aug 23
Utility
03rc4remwipx7smfvjt51alakcusac9f1im94k8b qqp3gkm4almb4wt0aiy
30 Nov 23
Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering.
Chun-An Lin, Kuo-Pi Tseng, Tzu-Chieh Su
Filed: 9 Aug 23
Utility
omr3h7zf4q37ham ulkkyf
30 Nov 23
A method includes forming isolation regions extending into a semiconductor substrate.
Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
Filed: 28 Jul 23
Utility
y2ahb3pw8790sabu1uminwtyg440sjsrvzfe01qi p6th1k
30 Nov 23
A semiconductor device includes a semiconductor layer.
Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
Filed: 4 Aug 23
Utility
xm7fik12m2ljaomxqxjfk9opl 561tp6s0m1ct6z2lolqs8rlkalgr
30 Nov 23
The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device.
Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
Filed: 7 Aug 23
Utility
p9js79djwjzxuv d01tnnktemcybe7gg4enb5966p63ot38r1nwtnw
30 Nov 23
A semiconductor structure includes a power rail; an isolation structure over the power rail; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature; one or more channel layers over the isolation structure and connecting the first and the second S/D features; a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail.
Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
Filed: 7 Aug 23
Utility
m6jfpknf45m659utxf zwan
30 Nov 23
Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials.
Shahaji B. More, Shih-Chieh Chang
Filed: 9 Aug 23
Utility
huf1jjooav s8e6dcdz6snldqnwgw3rb28l2jrs
30 Nov 23
A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.
Chia-Ta Yu, Sheng-Chen Wang, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
Filed: 26 Jul 23
Utility
n8i63vm5fclrd32s64cxkfd9ci9
30 Nov 23
In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin.
Chia-Chi YU, Jui Fu HSIEH, Yu-Li LIN, Chih-Teng LIAO, Yi-Jen CHEN
Filed: 9 Aug 23
Utility
2s35k3dbsz6df7s6o5cnnig2196yctpun17a5efl3j7jxhxwd7b8w
30 Nov 23
A system and methods of manufacturing semiconductor devices is described herein.
Chia-Ao Chang, Pei-Ren Jeng, Chii-Horng Li, Yee-Chia Yeo
Filed: 9 Aug 23
Utility
19tc6b7u50oej75ijmw0itukm5t4fc03k8vfafhm97bjzy71
30 Nov 23
A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell.
Wei-Chih KAO, Hsin-Che CHIANG, Chun-Sheng LIANG, Kuo-Hua PAN
Filed: 10 Aug 23
Utility
f7v3amck9tbpq9atxk2veekdtl9t xxl24fy9hew0mgzo
30 Nov 23
A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer.
Te-Yang Lai, Che-Hao Chang, Chi On Chui
Filed: 10 Aug 23
Utility
6hswippb3kkwvndun06vu xz1xl7flpcc11e72mcbg6514voss8fm2qd6
30 Nov 23
Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided.
Jenn-Gwo Hwu, Chien-Shun Liao
Filed: 28 Jul 23
Utility
0g85st5nniybyi6zgnsajm abv938fyf803rq3eg1aamflev6jbnogpw
30 Nov 23
Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate.
Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
Filed: 3 Aug 23
Utility
jy8h9pbl8dij7cphb139pbt4fdmy92bxncffglsacsen3fjcda
30 Nov 23
A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.
Pravanshu Mohanta, Wei-Ting Chang, Ching Yu Chen, Jiang-He Xie
Filed: 25 May 22
Utility
m7nw94b6 mscoyt9rmiwgac
30 Nov 23
A device and methods of forming the same are described.
Gerben Doornbos, Oreste Madia, Georgios Vellianitis, Marcus Johannes Henricus Van Dal
Filed: 29 May 22
Utility
0l4b9ypa3ei1 2fmn37qs9nq1kpe391i
30 Nov 23
The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device.
CHUN-YEN PENG, CHIH-YU CHANG, BO-FENG YOUNG, TE-YANG LAI, SAI-HOOI YEONG, CHI ON CHUI
Filed: 28 Jul 23
Utility
7l54d8nelcun4jk5e1u gb2r1wd
30 Nov 23
A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer.
Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
Filed: 9 Aug 23