1577 patents
Page 13 of 79
Utility
Semiconductor Device and Method of Manufacturing the Same
2 Mar 23
A semiconductor substrate has a surface and a convex portion projecting upward from the surface.
Makoto KOSHIMIZU, Yasutaka NAKASHIBA, Tohru KAWAI
Filed: 19 Jul 22
Utility
Semiconductor Device
2 Mar 23
An interlayer dielectric layer covers an electric fuse element.
Naohito SUZUMURA, Kenichiro SONODA, Hideaki TSUCHIYA
Filed: 15 Jun 22
Utility
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2 Mar 23
A performance of a semiconductor device is improved.
Tatsuaki TSUKUDA
Filed: 25 Jul 22
Utility
pqororvkf2fn5tbo3h5ccv58t0ofj04nfnedtbnvonaxda84cs6xdgq
2 Mar 23
The present invention suppresses an increase in manufacturing cost and reduces switching noise.
Takehiro UEDA
Filed: 31 Aug 21
Utility
bg1m0jgd8b2q0um1mu0vz9evtvujv62t8rld0nxhmc2a
2 Mar 23
An electric fuse element has a first portion, a second portion arranged on one end of the first portion, and a third portion arranged on the other end of the first portion.
Naohito SUZUMURA, Hiromichi TAKAOKA, Kenichiro SONODA, Hideaki TSUCHIYA, Yasutaka NAKASHIBA
Filed: 23 Jun 22
Utility
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2 Mar 23
A semiconductor device capable of shortening an erasing time and suppressing deterioration of retention characteristics is provided.
Shinji INOUE
Filed: 27 Jul 22
Utility
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2 Mar 23
Characteristics of a semiconductor device having a non-volatile memory are improved.
Yanzhe WANG
Filed: 30 Aug 21
Utility
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2 Mar 23
A first conductor pattern is formed on a semiconductor substrate of a scribing region via an insulating film.
Yukio TAKAHASHI
Filed: 21 Jul 22
Utility
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2 Mar 23
When one of CPUs that perform a lock step operation fails and the failure type is an SW failure, the semiconductor device copies information held by an SR and a GR of the CPU operating normally to the CPU with the SW failure, thereby continuing a process without stopping the lock step operation.
Takayuki OOTANI
Filed: 1 Aug 22
Utility
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2 Mar 23
A semiconductor device includes a first semiconductor chip in which a first multilayer wiring structure including a first coil and a second coil is formed and a second semiconductor chip in which a second multilayer wiring structure including a third coil and a fourth coil is formed.
Yasutaka NAKASHIBA, Hiroshi MIYAKI
Filed: 12 Aug 22
Utility
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2 Mar 23
A wiring substrate includes: a first insulating layer; a ground plane formed on the first insulating layer; a second insulating layer formed on the first insulating layer such that the ground plane is covered with the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer formed on the second insulating layer such that the first signal wiring is covered with the third insulating layer; and a second signal wiring formed on the third insulating layer and electrically connected with the first signal wiring.
Keita TSUCHIYA, Shuuichi KARIYAZAKI, Kazuhiro MITAMURA
Filed: 15 Jun 22
Utility
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2 Mar 23
A performance of a memory cell including a ferroelectric film is improved.
Tadashi YAMAGUCHI
Filed: 23 Jun 22
Utility
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28 Feb 23
An interlayer insulating film has via holes.
Toshikazu Hanawa, Kazuhide Fukaya, Makoto Koshimizu
Filed: 30 Oct 19
Utility
r60j53zshwo2qxd8885oxhndh6y7lt7ul
23 Feb 23
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede.
Takeshi Kawamura
Filed: 28 Oct 22
Utility
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23 Feb 23
A semiconductor device and a method of manufacturing the semiconductor device to achieve both of a high breakdown voltage and a low on resistance are provided.
Makoto KOSHIMIZU, Yasutaka NAKASHIBA
Filed: 28 Jul 22
Utility
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16 Feb 23
A semiconductor device includes a first control unit, a second control unit, a random number generator, a first memory in which random numbers generated by the random number generator are stored, an encryption engine configured to perform encryption and decryption processes by using the random numbers stored in the first memory, and a second memory in which information related to random number generation is stored.
Yuki MORI
Filed: 6 Jul 22
Utility
83v1ma92s68i0aje6j9j5y54r5y2qiwmlklpm16ymbwtors4fs73q
16 Feb 23
A torque map generation system includes a motor, an inverter that drives the motor, a controller that controls the inverter, a torque sensor coupled to the motor, a power analyzer coupled to the torque sensor and a torque map generator that measures a current vector value of the motor by switching a MTPA (Maximum Torque Per Ampere) method and a square wave method based on a voltage utilization ratio of the inverter, wherein the torque map generator utilizes a measurement result by the MTPA method when the torque map generator uses the square wave method.
Chengzhe LI
Filed: 11 Aug 21
Utility
9c4jvzn5jf2cv9lvluu6zr7yyehpxggy4rg26xzmzc6d8ptc2
14 Feb 23
The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data.
Sho Yamanaka, Toshiyuki Hiraki
Filed: 6 Aug 21
Utility
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9 Feb 23
A semiconductor device includes a plurality of word lines extending in a first direction in a plan view, a plurality of bit lines extending in a second direction orthogonal to the first direction in a plan view, and a plurality of memory cells arranged in matrix in the first direction and the second direction.
Tatsuyoshi MIHARA
Filed: 23 Jun 22
Utility
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9 Feb 23
Variations of characteristics of a semiconductor device provided with a power MOSFET having a super junction structure are suppressed, and reliability of the semiconductor device is improved.
Yasutaka NAKASHIBA, Masami SAWADA
Filed: 13 Jun 22