291 patents
Page 14 of 15
Utility
Method Of Programming A Split-Gate Flash Memory Cell With Erase Gate
26 Feb 20
A memory device with a memory cell and control circuitry.
Yuri Tkachev, Alexander Kotov, Nhan Do
Filed: 3 Dec 18
Utility
Dynamic Modification Of Programming Duration Based On Number Of Cells To Be Programmed In Analog Neural Memory Array In Deep Learning Artificial Neural Network
19 Feb 20
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 23 Aug 19
Utility
nhwf3d rr6rp6jblw4j705pq71gn6egi
19 Feb 20
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 24 Aug 19
Utility
a1u9zch2ktg81kj0ghw2 z5g2ssf136vglbn9lhsppcftigpj3pzqs
12 Feb 20
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 24 Aug 19
Utility
qbyg5y05o0qicfyqrfkgsbbu7n6rbuuyqvyqwo6qebv3boe
12 Feb 20
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 24 Aug 19
Utility
i7t7dfi7tq1bhi6tcu1vpbnrelgnd1wdw8srzw8gcmeg
29 Jan 20
Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 1 Oct 19
Utility
f231omwlfx1a1wek6kk48v4muskk5 h6mtyr4rkioss9lpp8x65064
27 Jan 20
An improved low-power sense amplifier for use in a flash memory system is disclosed.
Xiaozhou Qiang, Xiao Yan Pi, Kai Man Yue, Li Fang Bian
Filed: 29 Aug 18
Utility
zrfd04va4gene7wbqrwzv78j1zd8hxrqscwhu065fqo2f
15 Jan 20
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 2 Oct 18
Utility
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15 Jan 20
Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
Hieu Van Tran, Stanley Hong, Thuan Vu, Anh Ly, Hien Pham, Kha Nguyen, Han Tran
Filed: 2 Oct 18
Utility
69shxaim5by48yp6k muv7yec49ocwu4
15 Jan 20
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
Filed: 18 Sep 19
Utility
t5tqv3h0bw8t70jh5ahzf vydjudef2dqjb1j346vxapi6lrf44aie
13 Jan 20
Apparatus, and an associated method, for enhancing security and preventing hacking of a flash memory device.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 12 Oct 17
Utility
jk1f122jgb82qg68tjq6pf1ymf12vv9aa2ug cdcep2xoxkloozemvbyfzxj
8 Jan 20
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
Filed: 18 Sep 19
Utility
v438ay4 rj7qqxrf63sa5ljcryt8l5jm6levqh1llmamvaobom0j108jdw7
8 Jan 20
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
Filed: 18 Sep 19
Utility
fbdyu9lgjjhtyg6bsij8ejd9926fgx8z2z5vccx85lemfyq2
8 Jan 20
A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface.
SERGUEI JOURBA, CATHERINE DECOBERT, FENG ZHOU, JINHO KIM, XIAN LIU, NHAN DO
Filed: 4 Jul 18
Utility
f7ufjq79b6d4w88gndg7zwapejoxj22dhlzqgj4
8 Jan 20
A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 23 May 19
Utility
i80wxqn08vknbyuqo6 he0jpr7793kgulxzrmbauh4t7r6h
8 Jan 20
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins.
Feng Zhou, Jinho Kim, Xian Liu, Serguei Jourba, Catherine Decobert, Nhan Do
Filed: 19 Sep 19
Utility
hbxqm3wi5t0vbt18697 1zmfb7bjbqvnhl0gquqb2gt3h2bbt3tq6ys
30 Dec 19
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 22 Jul 18
Utility
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23 Dec 19
A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current.
Vipin Tiwari, Nhan Do, Hieu Van Tran
Filed: 30 Sep 18
Utility
new4ztbggx6nqf6wrsw0t99b63e14o0xigrbx3emyr6zcwrsap9
18 Dec 19
A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance.
Xiaozhou QIAN, Kai Man YUE, Guang Yan LUO
Filed: 29 Aug 18
Utility
xkks6vdlcu8mlll1hxvvuq56xtctcdjaanyszlc3x878ws88ukc15sr1s
18 Dec 19
An improved low-power sense amplifier for use in a flash memory system is disclosed.
XIAOZHOU QIANG, XIAO YAN PI, KAI MAN YUE, LI FANG BIAN
Filed: 29 Aug 18