291 patents
Page 15 of 15
Utility
Address Fault Detection In A Flash Memory System
11 Dec 19
A system and method are disclosed for performing address fault detection in a flash memory system.
Hieu Van Tran, Xian Liu, Nhan Do
Filed: 25 Aug 19
Utility
Power Line Compensation for Flash Memory Sense Amplifiers
20 Nov 19
In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory.
Hieu Van Tran
Filed: 29 Jul 19
Utility
Split-Gate Flash Memory Array With Byte Erase Operation
20 Nov 19
A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.
Hsuan Liang, Jeng-Wei Yang, Man-Tang Wu, Nhan Do, Hieu Van Tran
Filed: 22 Jul 18
Utility
Method of Making Embedded Memory Device With Silicon-On-Insulator Substrate
13 Nov 19
A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate.
Jinho Kim, Xian Liu, Feng Zhou, Parviz Ghazavi, Steve Lemke, Nhan Do
Filed: 6 Aug 18
Utility
Method and Apparatus for High Voltage Generation for Analog Neural Memory In Deep Learning Artificial Neural Network
6 Nov 19
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Staniey Hong, Anh Ly, Vlpln Tlwarl, Nhan Do
Filed: 22 Jul 18
Utility
Method And Apparatus For Data Refresh For Analog Non-volatile Memory In Deep Learning Neural Network
6 Nov 19
Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 15 May 19
Utility
Split gate non-volatile memory cells and logic devices with FinFET structure, and method of making same
4 Nov 19
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins.
Feng Zhou, Jinho Kim, Xian Liu, Serguei Jourba, Catherine Decobert, Nhan Do
Filed: 18 Apr 18
Utility
Dynamic programming of advanced nanometer flash memory
28 Oct 19
An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
Filed: 24 Aug 17
Utility
Array of three-gate flash memory cells with individual memory cell read, program and erase
28 Oct 19
A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 16 Apr 19
Utility
Split Gate Non-volatile Memory Cells and Logic Devices with Finfet Structure, and Method of Making Same
23 Oct 19
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins.
FENG ZHOU, Jinho Kim, Xian Liu, Serguei Jourba, Catherine Decobert, Nhan Do
Filed: 18 Apr 18
Utility
Method and apparatus for data refresh for analog non-volatile memory in deep learning neural network
14 Oct 19
Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 24 May 18