291 patents
Page 11 of 15
Utility
Dynamic modification of programming duration based on number of cells to be programmed in analog neural memory array in deep learning artificial neural network
16 Nov 20
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 23 Aug 19
Utility
Programming of memory cell having gate capacitively coupled to floating gate
16 Nov 20
A memory device with memory cells each including source and drain regions with a channel region there between, a floating gate over a first channel region portion, a select gate over a second channel region portion, a control gate over the floating gate, and an erase gate over the source region.
Viktor Markov, Alexander Kotov
Filed: 11 Dec 18
Utility
Method of making split gate non-volatile flash memory cell
9 Nov 20
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
Filed: 18 Sep 19
Utility
Method of making split gate non-volatile flash memory cell
9 Nov 20
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
Filed: 18 Sep 19
Utility
Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory In Deep Learning Artificial Neural Network
4 Nov 20
Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells.
Hieu Van Tran, STEPHEN TRINH, THUAN VU, STANLEY HONG, VIPIN TIWARI, MARK REITEN, NHAN DO
Filed: 20 Jun 19
Utility
Output Array Neuron Conversion and Calibration for Analog Neural Memory In Deep Learning Artificial Neural Network
4 Nov 20
Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells.
Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 20 Jun 19
Utility
Temperature Compensation for Memory Cells In an Analog Neural Memory System Used In a Deep Learning Neural Network
4 Nov 20
Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array.
HIEU VAN TRAN, STEVEN LEMKE, NHAN DO, VIPIN TIWARI, MARK REITEN
Filed: 15 Jul 20
Utility
Decoding System and Physical Layout for Analog Neural Memory In Deep Learning Artificial Neural Network
28 Oct 20
Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed.
HIEU VAN TRAN, THUAN VU, STANLEY HONG, STEPHEN TRINH, ANH LY, HAN TRAN, KHA NGUYEN, HIEN PHAM
Filed: 2 Jul 19
Utility
Split gate non-volatile memory cells and logic devices with FINFET structure, and method of making same
26 Oct 20
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins.
Feng Zhou, Jinho Kim, Xian Liu, Serguei Jourba, Catherine Decobert, Nhan Do
Filed: 19 Sep 19
Utility
Precision Tuning for the Programming of Analog Neural Memory In a Deep Learning Artificial Neural Network
21 Oct 20
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
HIEU VAN TRAN, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
Filed: 1 Jul 20
Utility
Neural network classifier using array of four-gate non-volatile memory cells
12 Oct 20
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
Level shifter for integrated circuit
12 Oct 20
An improved level shifter for use in integrated circuits is disclosed.
Ryan Mei, Claire Zhu, Xiaozhou Qian
Filed: 30 Dec 19
Utility
FinFET-based split gate non-volatile flash memory with extended source line FinFET, and method of fabrication
5 Oct 20
A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 2 Dec 18
Utility
Method of making embedded memory device with silicon-on-insulator substrate
28 Sep 20
A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate.
Jinho Kim, Xian Liu, Feng Zhou, Parviz Ghazavi, Steven Lemke, Nhan Do
Filed: 6 Aug 18
Utility
Adaptive high voltage circuitry and methods for programming operations in an analog neural memory array in a deep learning artificial neural network
28 Sep 20
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 24 Aug 19
Utility
Flash Memory Cell and Associated High Voltage Row Decoder
9 Sep 20
The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells.
Hieu Van Tran, Anh Ly, Thuan Vu
Filed: 19 May 20
Utility
Analog Neural Memory System for Deep Learning Neural Network Comprising Multiple Vector-by-matrix Multiplication Arrays and Shared Components
26 Aug 20
Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
Filed: 17 Jan 20
Utility
Architectures and layouts for an array of resistive random access memory cells and read and write methods thereof
24 Aug 20
Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed.
Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
Filed: 10 Sep 17
Utility
Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network
24 Aug 20
Numerous embodiments are disclosed for providing temperature compensation and leakage compensation for an analog neuromorphic memory system used in a deep learning neural network.
Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
Filed: 6 Nov 18
Utility
High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
17 Aug 20
An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays.
Hieu Van Tran, Vipin Tiwari, Nhan Do, Steven Lemke, Santosh Hariharan, Stanley Hong
Filed: 28 Nov 17