291 patents
Page 9 of 15
Utility
Circuitry to Compensate for Data Drift In Analog Neural Memory In an Artificial Neural Network
8 Jul 21
Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system.
Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
Filed: 26 Mar 20
Utility
Precise Data Tuning Method and Apparatus for Analog Neural Memory In an Artificial Neural Network
8 Jul 21
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, STEVEN LEMKE, NHAN DO, MARK REITEN
Filed: 25 Feb 21
Utility
CorrectedProgramming Circuit and Method For Flash Memory Array
8 Jul 21
An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
Filed: 17 Sep 19
Utility
Method Of Forming A Device With Split Gate Non-volatile Memory Cells, HV Devices Having Planar Channel Regions And FINFET Logic Devices
24 Jun 21
A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 20 Dec 19
Utility
Low voltage level shifter for integrated circuit
15 Jun 21
An improved level shifter is disclosed.
Ryan Mei, Xiaozhou Qian, Hieu Van Tran, Claire Zhu
Filed: 2 Apr 20
Utility
Output Circuits for an Analog Neural Memory System for Deep Learning Neural Network
10 Jun 21
Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 22 Feb 21
Utility
Virtual Ground Non-volatile Memory Array
10 Jun 21
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates.
Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
Filed: 18 Feb 21
Utility
Power line compensation for flash memory sense amplifiers
8 Jun 21
In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory.
Hieu Van Tran
Filed: 30 Jul 19
Utility
Low Voltage Level Shifter For Integrated Circuit
3 Jun 21
An improved level shifter is disclosed.
Ryan Mei, XIAOZHOU QIAN, HIEU VAN TRAN, CLAIRE ZHU
Filed: 2 Apr 20
Utility
Method of improving read current stability in analog non-volatile memory using final bake in predetermined program state
25 May 21
A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state.
Viktor Markov, Alexander Kotov
Filed: 27 Feb 20
Utility
Method of forming split gate memory cells with thinned tunnel oxide
25 May 21
A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge.
Jinho Kim, Elizabeth Cuevas, Parviz Ghazavi, Bernard Bertello, Gilles Festes, Catherine Decobert, Yuri Tkachev, Bruno Villard, Nhan Do
Filed: 4 Feb 20
Utility
Flash memory cell and associated high voltage row decoder
18 May 21
The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells.
Hieu Van Tran, Anh Ly, Thuan Vu
Filed: 20 May 20
Utility
Precise Programming Method And Apparatus For Analog Neural Memory In An Artificial Neural Network
13 May 21
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 23 Jan 20
Utility
Verifying or Reading a Cell In an Analog Neural Memory In a Deep Learning Artificial Neural Network
13 May 21
Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 17 Dec 20
Utility
Memory cell with floating gate, coupling gate and erase gate, and method of making same
4 May 21
A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between.
Catherine Decobert, Hieu Van Tran, Nhan Do
Filed: 3 Dec 18
Utility
Method of improving read current stability in analog non-volatile memory by limiting time gap between erase and program
27 Apr 21
A memory device having non-volatile memory cells and a controller.
Viktor Markov, Alexander Kotov
Filed: 27 Feb 20
Utility
Input and Digital Output Mechanisms for Analog Neural Memory In a Deep Learning Artificial Neural Network
22 Apr 21
Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
Filed: 23 Dec 20
Utility
Input and Digital Output Mechanisms for Analog Neural Memory In a Deep Learning Artificial Neural Network
1 Apr 21
Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
Filed: 14 Dec 20
Utility
Precision Tuning for the Programming of Analog Neural Memory In a Deep Learning Artificial Neural Network
25 Mar 21
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 19 Sep 19
Utility
Temperature Compensation In an Analog Memory Array by Changing a Threshold Voltage of a Selected Memory Cell In the Array
25 Mar 21
Numerous embodiments are disclosed for providing temperature compensation in an analog memory array.
Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
Filed: 11 Nov 20