291 patents
Page 6 of 15
Utility
Analog neural memory array in artificial neural network with substantially constant array source impedance with adaptive weight mapping and distributed power
7 Jun 22
Numerous embodiments of analog neural memory arrays are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Vipin Tiwari
Filed: 6 Aug 20
Utility
Word Line and Control Gate Line Tandem Decoder for Analog Neural Memory In Deep Learning Artificial Neural Network
2 Jun 22
Various embodiments of tandem row decoders are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 15 Feb 22
Utility
Deep Learning Neural Network Classifier Using Non-volatile Memory Array
12 May 22
An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses.
FARNOOD MERRIKH BAYAT, XINJIE GUO, DMITRI STRUKOV, NHAN DO, HIEU VAN TRAN, VIPIN TIWARI, MARK REITEN
Filed: 21 Jan 22
Utility
Self-timed sensing architecture for a non-volatile memory system
10 May 22
A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed.
Massimiliano Frulio
Filed: 11 Nov 20
Utility
Split Gate Non-volatile Memory Cells, HV and Logic Devices with Finfet Structures, and Method of Making Same
5 May 22
A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby.
Guo Xiang Song, CHUNMING WANG, LEO XING, XIAN LIU, NHAN DO
Filed: 19 Jan 21
Utility
Method of making memory cells, high voltage devices and logic devices on a substrate with silicide on conductive blocks
3 May 22
A method of forming a semiconductor device includes recessing the upper surface of first and second areas of a semiconductor substrate relative to the third area of the substrate, forming a pair of stack structures in the first area each having a control gate over a floating gate, forming a first source region in the substrate between the pair of stack structures, forming an erase gate over the first source region, forming a block of dummy material in the third area, forming select gates adjacent the stack structures, forming high voltage gates in the second area, forming a first blocking layer over at least a portion of one of the high voltage gates, forming silicide on a top surface of the high voltage gates which are not underneath the first blocking layer, and replacing the block of dummy material with a block of metal material.
Chunming Wang, Jack Sun, Xian Liu, Leo Xing, Nhan Do, Andy Yang, Guo Xiang Song
Filed: 25 Feb 21
Utility
Wear Leveling In Eeprom Emulator Formed of Flash Memory Cells
28 Apr 22
The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM.
Guangming Lin, Xiaozhou Qian, Xiao Yan Pl, Vipin Tiwari, Zhenlin Ding
Filed: 7 Jan 22
Utility
Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same
26 Apr 22
A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions.
Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing, Nhan Do
Filed: 19 Jan 21
Utility
Four gate, split-gate flash memory array with byte erase operation
26 Apr 22
A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.
Hsuan Liang, Man Tang Wu, Jeng-Wei Yang, Hieu Van Tran, Lihsin Chang, Nhan Do
Filed: 6 Feb 20
Utility
Method of forming a device with planar split gate non-volatile memory cells, high voltage devices and FinFET logic devices
26 Apr 22
A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.
Chunming Wang, Guo Xiang Song, Leo Xing, Jack Sun, Xian Liu, Nhan Do
Filed: 19 Jan 21
Utility
Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same
26 Apr 22
A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing, Nhan Do
Filed: 2 Feb 21
Utility
Deep learning neural network classifier using non-volatile memory array
19 Apr 22
An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 12 May 17
Utility
Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noise
19 Apr 22
A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate.
Viktor Markov, Alexander Kotov
Filed: 29 Jun 20
Utility
Split-gate, 2-BIT Non-volatile Memory Cell with Erase Gate Disposed Over Word Line Gate, and Method of Making Same
31 Mar 22
A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions.
CHUNMING WANG, XIAN LIU, GUO XIANG SONG, LEO XING, NHAN DO
Filed: 19 Jan 21
Utility
Split-gate Non-volatile Memory Cells with Erase Gates Disposed Over Word Line Gates, and Method of Making Same
31 Mar 22
A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing, Nhan Do
Filed: 2 Feb 21
Utility
Word line and control gate line tandem decoder for analog neural memory in deep learning artificial neural network
29 Mar 22
Various embodiments of tandem row decoders are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 25 Nov 20
Utility
Method of Forming a Device with Planar Split Gate Non-volatile Memory Cells, High Voltage Devices and Finfet Logic Devices
24 Mar 22
A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.
Chunming Wang, Guo Xiang Song, Leo Xing, Jack Sun, Xian Liu, Nhan Do
Filed: 19 Jan 21
Utility
Neural network classifier using array of three-gate non-volatile memory cells
8 Mar 22
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 11 Apr 19
Utility
Neural network classifier using array of stacked gate non-volatile memory cells
8 Mar 22
A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 11 Apr 19
Utility
Concurrent Write and Verify Operations In an Analog Neural Memory
3 Mar 22
Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed.
Hieu Van Tran
Filed: 2 Mar 21